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**A note on VESA support of 486 chipsets.
Many chipsets state that they support VESA local bus. In some cases
these actually implement VLB somewhat like PCI, where it is entirly
decoupled from the CPU bus. Chipsets that do not state they work with
VLB, may be found on motherboards that contain VLB slots. VLB
is *basically* The 486 CPU pinout in a slot form. Unless these
m/boards contain some additional chips, there VLB implementation is
directly coupled to the CPU.
**Datasheets:...
*_IBM...
*ACC Micro...
*ALD...
*ALi...
**M1521/23 Aladdin III 50-66MHz <Nov96
***Info:...
***Configurations:...
***Features:...
**M1531/33/43 Aladdin IV & IV+ 50-83.3MHz <05/28/97...
**M1541/42/33/43 Aladdin V & V+ 50-100MHz ?...
**M1561/43/35D Aladdin 7 ArtX [no datasheet, some info] 11/08/99...
**M6117 386SX Single Chip PC <97
***Notes:...
***Info:...
***Versions:...
***Features:
o Static Intel 386SX compatible Core
- Operating Power Supply 5.0V
- Operating frequency 25Mhz to 40Mhz
o Memory Controller
- Supports EDO DRAM
- Supports on board memory size up to 16M bytes for 386SX or 64M
bytes upgrade system using 256K, 512K, 1M, 4M or 16M SIMMs
- Supports up to 4-bank DRAM interface
- Page interleave DRAM access for FP mode
- Programmable shadow RAM from A to B segment in 128K byte and C
to F segment in 32K byte unit
- Provides "RAS only" refresh or "CAS before RAS” refresh types
- Parity generation and checking
o Peripheral Interface
- Includes 2 cascaded 8237 DMA controllers
- Includes 1 74612 memory mapper
- Includes 2 cascaded 8259 interrupt controllers
- Includes 1 8254 programming counter
o ISA Interface
- Executes cycles for requests from CPU, DMA and ISA bus master
- Assembles or de-assembles data for multiple bus cycle or
unmatched data width
- Generates refresh signals to ISA slots during DRAM refresh
cycles
o Built-in RTC
- Internal Real Time Clock that provides 128 byte CMOS RAM
o Programmable 2 channels chip select
- Provide chip select for memory or I/O device without external
address decode random logic
o Built-In PS2/AT Keyboard Controller
- Internal PS2/AT keyboard controller and mouse
o PMU interface
- Supports CPU SMM mode, SMI feature
- Supports APM control
- Provides External Suspend mode switch
- Provides four (4) system states for power saving (On, Doze,
Standby, Suspend)
- Supports RTC alarm wake up control
o Expandable GPI/O signals
- Provides sixteen External power control input and output signals
- Provides sixteen independent pin for general purpose input and
output signals
o Watchdog timer
- When timer times out , a system reset or NMI or IRQ happens
o IDE interface
- Provides a decoder for external IDE connection
o Packaging
- 208-pin PQFP package
**
**Support Chips:
**M1535/D South Bridge ?...
**
**May not exist:...
**Later Chipsets:...
**Other:...
*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
*Contaq . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82495DX/490DX DX CPU-Cache Chip Set <Sep91
***Notes:...
***Info:...
***Configurations:...
***Features:...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...
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