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**Spelling errors/mistyped words
Yes, I  know there are  spelling errors,  and things are  mistyped. It
seems no matter  how hard I try  my fingers hit 't'  twice when typing
'compatible' rendering it 'compattible' numerous, (thousands actually)
times.  I  don't have the  time or the will  to check the  spelling of
everything. Basic spell checking has been peformed. Please let me know
if  there is  anything that  would lead  to incorrect  information, or
something  is so  mangled  that  it needs  revising.  But  if you  can
basically  understand  what was  intended,  just  cope with  it.  Just
cope:-)

BTW, "110" port is  an "I/O" port that has been OCRed  badly, as is an
"1/0" port.

**Info needed on:...
**A note on VESA support of 486 chipsets....
**Datasheets:...
*_IBM...
*ACC Micro...
*ALD...
*ALi...
*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
*Contaq  . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94
***Notes:...
***Info:...
***Configurations:...
***Features:...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
*UMC...
**UM82152      Cache Controller (AUStek A38152 clone)              <91
***Info:
The  UM82152 is a  high-performance cache  controller for  Intel 80386
based   systems  and   provides   high  levels   of  integration   and
functionality.  It interfaces  directly  to the  80386; no  additional
support  logic  is required.   A  complete  32-kilobyte  cache can  be
designed with just one UM82152 and four 8K by 8-bit static RAMs.

The  UM82152 architecture  enables easy  design-in with  current speed
versions  of  the  80386,  and  simple  migration  to  faster  version
processors with no alteration to system or memory design.

The 80386,  operating in  pipelined mode with  the UM82152,  runs with
zero  wait states during  a cache  hit (requested  data is  present in
cache). If  the data is not  present (cache miss), it  is fetched from
main  memory by  the  UM82152.  This  approach  yields the  high-speed
performance  of fast  SRAMs for  code and  data most  frequently used,
while  providing design  economies (such  as board  space  savings and
lower component costs)  by storing infrequently used code  and data in
slower  dynamic RAM (with  cycle times  greater than  125 nanoseconds)
that  can  be  located  in  large  memory  banks  either  on-board  or
off-board.

The reduced system bus  traffic inherent in the UM82152 implementation
produces system performance gains by  freeing the bus for use by other
devices.

***Versions:...
***Features:...
**UM82C852     Multi I/O For XT                                    <91...
**UM82C206     Integrated Peripheral Controller                    <91...
**UM82c45x     Serial/Parallel chips                                 ?...
**Other chips:...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...