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**450NX  (?)            06/29/98:
Chips:
[82454NX] (PXB) [82453NX] (MUX) 
[82452NX] (RCG) [82451NX] (MIOC) 
[82371EB] (PIIX4E),                            
CPUs:          Single/Dual/Quad P-II Xeon/P-III Xeon
DRAM Types:    FPM EDO 2-way Interleave 4-way Interleave
Mem Rows:      8
DRAM Density:  16Mbit 64Mbit
Max Mem:       8GB
ECC/Parity:    Both
AGP speed:     N/A
Bus Speed:     100
PCI Clock/Bus: 1/3


**?????  (Profusion)    c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
**SL6012  Memory Mapper for PC-AT (74LS612 compatible)          <Jul87
***Info:...
***Versions:...
***Features:...
**SL9010  System Controller (80286/80386SX/DX, 16/20/25MHz)     <oct88...
**SL9020  Data Controller                                       <oct88...
**SL9025  Address Controller                                    <oct88...
**SL9090  Universal PC/AT Clock Chip                            <oct88...
**SL9250  Page Mode Memory Controller (16/20MHz 8MB Max)        <oct88...
**SL9350  Page Mode Memory Controller (16/20/25MHz 16MB Max)    <oct88...
**Other:...
*Motorola...
*OPTi...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
*UMC...
**UM82C210     386SX/286 AT Chip Set                               <91
***Info:...
***Configurations:...
***Features:...
**UM82C3xx     Twinstar & UM82C336F/N & UM82C39x [no datasheet]      ?...
**UM82C380     386 HEAT PC/AT Chip Set                             <91...
**UM82C480     386/486 PC Chip Set                                 c91
***Info:...
***Configurations:...
***Features:
o   100% IBM PC/AT compatible
o   Supports 80386 CPU running at 25/33/40 MHz
o   Supports 80486 CPU running at 25/33/40/50 MHz in 1x clock
o   Supports Intel 80387 / Weitek 3167 / Weitek 4167 Floating Point 
    Coprocessors
o   Built-in cache controller:
    - Direct-mapped organization with write-back operation
    - 0 wait state for cache hit
    - Flexible cache size: 32/64/128/256/512/1024 KB
    - Hidden DRAM refresh to boost system performance
    - built-in registers to support three independent non-cacheable 
      regions
    - Support cache line fill as well as 80486 burst mode
    - Support Automatic Memory Size Detection
o   Sophisticated DRAM controller:
    - Supports Fast/Standard page mode
    - Supports 4 banks CPU speed DRAM with memory size up to 64MB
    - Supports mixable 256Kx9, 1Mx9, 4Mx9 DRAM modules
    - Programmable DRAM wait states
    - Supports 256KB or 384KB (A to F segments of first 1MB) 
      relocation to the top of DRAM memory
o   Supports sophisticated Shadow RAM for video and system BIOS (C, D,
    E, F segments)
o   Supports first GATE A20 and fasy CPU RESET to optimize OS/2 
    operations
o   Synchronous AT bus clock with programmable clock (divided by 2, 3,
    4, 5, 6)
o   Programmable CPU clock (divided by 1, 2, 3, 4)
o   Support 256KB/512KB/1MB EPROMs with single or double EPROM BIOS 
    configuration

**UM82C493/491 ??????????????? [no datasheet]                        ?...
**UM8498/8496  486 VL Chipset  "Super Energy Star Green"[no dsheet]c94...
**UM8881/8886  HB4 PCI Chipset "Super Energy Star Green"[no dsheet]c94...
**UM8890       Pentium chipset [no datasheet]                        ?...
**
**Support Chips:
**UM82152      Cache Controller (AUStek A38152 clone)              <91...
**UM82C852     Multi I/O For XT                                    <91...
**UM82C206     Integrated Peripheral Controller                    <91...
**UM82c45x     Serial/Parallel chips                                 ?...
**Other chips:...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...