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**Spelling errors/mistyped words
Yes, I  know there are  spelling errors,  and things are  mistyped. It
seems no matter  how hard I try  my fingers hit 't'  twice when typing
'compatible' rendering it 'compattible' numerous, (thousands actually)
times.  I  don't have the  time or the will  to check the  spelling of
everything. Basic spell checking has been peformed. Please let me know
if  there is  anything that  would lead  to incorrect  information, or
something  is so  mangled  that  it needs  revising.  But  if you  can
basically  understand  what was  intended,  just  cope with  it.  Just
cope:-)

BTW, "110" port is  an "I/O" port that has been OCRed  badly, as is an
"1/0" port.

**Info needed on:...
**A note on VESA support of 486 chipsets....
**Datasheets:...
*_IBM...
*ACC Micro...
*ALD...
*ALi...
*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
*Contaq  . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94
***Notes:...
***Info:...
***Configurations:...
***Features:...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
**SL82C470   'Mozart' 486/386 EISA chipset                     c:Dec91
***Info:...
***Configurations:...
***Features:
o   100% EISA compatible
o   20/25/33/50 MHz 80486 DX/SX CPU operation
o   25/33/40 Mhz 80386DX CPU Operation
o   Integrated write back cache controller with built-in tag comparator
o   Concurrent CPU-cache and EMA/master operations with bus snooping
o   Only ten TTL components are required
o   Complete EISA system can be built on a baby AT sized motherboard
o   Flexible cache size from 64KB to 1MB
o   Page mode DRAM operation supporting 1 to 4 banks up to 256MB
o   Video/system BIOS, shadowing and caching
o   Supports both conventional and concurrent configurations
o   Inclusive secondary cache for snoop filtering
o   Synchronous EISA bus clock
o   Transparent Gate A20 and CPU reset
o   CPU local bus device support
o   Supports 80387, 80487SX and Weitek 3167/4167 co-processors
o   Decoupled refresh without holding CPU
o   Staggered DRAM refresh to minimize power supply noise
o   Rlch set of register options to allow customization
o   Three 160-pin PQFP packages in low power and high speed 0.8um CMOS 
    Technology
**SL82C490   'Wagner' 486?              [no datasheet]               ?...
**SL82C550   'Rossini' Pentium          [no datasheet]            c:95...
**
**Support Chips:
**SL82C365    Cache Controller (for 386DX/SX)                     c:91...
**SL82C465    Cache Controller (for 486/386DX/SX)                 c:91...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...