[Home] [This version is outdated, a new version is here]
*Title...
*Search:...
*Read Me/FAQ/General Info...
*_IBM...
*ACC Micro...
*ALD...
*ALi...
*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
*Contaq  . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**?????  (Profusion)    c:99
Chips:         
Memory Access Controller (MAC)  
Data Interface Buffer (DIB)
CPUs:          8x P-III Xeon Oct
DRAM Types:    SDRAM PC100 2-way Interleave dual channel
Max Mem:       32GB
ECC/Parity:    ECC
AGP speed:     N/A
Bus Speed:     100
PCI Clock/Bus: 1/3 PCI-66/64



**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
**85C471/407     Green PC ISA-VLB 486 Single Chip                  <94
***Info:
The  SiS85C47l, single chip  controller supports  Intel's 80486DX2/DX/
SX/SL Enhanced,  P24D/P24T/P24C CPU,  Cyrix's Cx486S2 (M6/M7)  CPU and
AMD's Am486DXL/DXLZ CPU.

The Si885C471 is a high performance, 100% PC/AT compatible single chip
controller,  designed for  cached/non-cached P24D/P24T/P24C,  M6/M7 or
486 PC systems. The high integration of the powerful cache controller,
the DRAM controller, the CPU  interfaces, the bus controller, the data
buffers and the peripheral controllers provides an easy and economical
solution for compact board manufacturing.

In addition to supporting burst reads  for the cache line fills of the
CPU, the  SiS85C47l is  capable of accepting  burst write data  of the
CPU's internal  cache dirty line(s) during CPU  write-back cycles. The
support of the  CPU burst write cycle is  optional through the control
of the Configuration Registers.  The SiS85C471 supports the cache size
up to l MB and the DRAM size up to 128 MB.

The SiS85C471  has a built-in  cache controller which  supports direct
mapped write-through/write-back  cache. The programmable  AT-bus clock
supports are compatible with  AT-bus timing requirements for different
PC systems.

In  addition, the  local bus  interfaces, the  integration of  the DMA
Controllers, Interrupt Controllers and Timers/Counters are designed to
be a higher performance, more compact, and more cost-effective product
for  a P24D/PZ4T/PZ4C,  486SX/DX/DX2/SL-Enhanced, Am486DXL/DXLZ,  or a
Cx48682 (M6/M7) PC/AT system.

The  SiS85C47I  provides power  saving  features  to allow  a  system,
through the  control of BIOS, to  reduce the CPU clock  frequency from
50MHz down to 0 MHz(STOP CLOCK) when the system is idle.

To support the SL-Enhanced  486, M6/M7, P24D/P24T/P24C's Am486DXL/DXL2
STPCLK/SMI features,  the SiS85C47l also implements  the corresponding
logics to support STPCLK /SMI for power saving.

The  SiSSSC471  supports the  VL-Bus  applications  including (1)  CPU
accesses VL-Bus  targets, (2) VL-Bus master  mode, and (3)  DMA or ISA
master accesses VL-Bus targets.

The  SiS85C471  provides  flexible  ways  in  configuring  the  system
depending   on  whether   cache  or   VESA  local   bus   masters  are
supported. The  different configurations require  different numbers of
external components.


***Configurations:...
***Features:...
**85C496/497     486-VIP 486 Green PC VESA/ISA/PCI Chipset         <95...
**85C501/502/503 Pentium/P54C PCI/ISA Chipset                <01/09/95...
**5101/5102/5103 Pentium/P54C PCI/ISA Chipset                <04/02/95
***Notes:...
***Info:...
***Configurations:...
***Features:...
**5120           Pentium PCI/ISA Chipset (Mobile)            <01/28/97...
**5501/5502/5503 Pentium/P54C PCI/ISA Chipset                <04/02/95...
**5511/5512/5513 Pentium PCI/ISA                             <06/14/95...
**5571           (Trinity) Pentium PCI/ISA Chipset (75MHz)   <12/09/96...
**5581/5582      (Jessie)  Pentium PCI/ISA Chipset (75MHz)   <04/15/97...
**5591/5592/5595 (David)   Pentium PCI A.G.P. Chipset        <01/09/98...
**5596/5513      (Genesis) Pentium PCI Chipset               <03/26/96...
**5597/5598      (Jedi)    Pentium PCI/ISA Chipset           <04/15/97...
**530/5595       (Sinbad) Host, PCI, 3D Graphics & Mem. Ctrl.<11/10/98...
**540            (Spartan) Super7 2D/3D Ultra-AGP Single C.S.<11/30/99...
**55x            SoC (System-on-chip)                        <03/14/02...
**
**Support chips:
**85C206     Integrated Peripheral Controller [no datasheet]         ?...
**5595       Pentium PCI System I/O                          <12/24/97...
**950        LPC I/O                                         <07/16/99...
**Other:...
**PII/III/Pro...
**Athlon etc...
*Symphony...
**SL82C470   'Mozart' 486/386 EISA chipset                     c:Dec91
***Info:...
***Configurations:...
***Features:...
**SL82C490   'Wagner' 486?              [no datasheet]               ?...
**SL82C550   'Rossini' Pentium          [no datasheet]            c:95...
**
**Support Chips:
**SL82C365    Cache Controller (for 386DX/SX)                     c:91...
**SL82C465    Cache Controller (for 486/386DX/SX)                 c:91...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...

(c) Copyright mR_Slugs Warehouse - All rights Reserved