[Home] [This version is outdated, a new version is here]
*Title...
*Search:...
*Read Me/FAQ/General Info...
**Spelling errors/mistyped words
Yes, I  know there are  spelling errors,  and things are  mistyped. It
seems no matter  how hard I try  my fingers hit 't'  twice when typing
'compatible' rendering it 'compattible' numerous, (thousands actually)
times.  I  don't have the  time or the will  to check the  spelling of
everything. Basic spell checking has been peformed. Please let me know
if  there is  anything that  would lead  to incorrect  information, or
something  is so  mangled  that  it needs  revising.  But  if you  can
basically  understand  what was  intended,  just  cope with  it.  Just
cope:-)

BTW, "110" port is  an "I/O" port that has been OCRed  badly, as is an
"1/0" port.

**Info needed on:...
**A note on VESA support of 486 chipsets....
**Datasheets:...
*_IBM...
*ACC Micro...
*ALD...
*ALi...
*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
*Contaq  . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94
***Notes:...
***Info:...
***Configurations:...
***Features:...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
**82c801         SCWB2 DX Single Chip Solution                    c:92
***Notes:...
***Info:...
***Configurations:...
***Features:
o   Supports 486 SX/DX/DX2 and 487SX 
o   Single chip PC/AT solution: one 208 pin CMOS plastic flat package 
o   1 X and 2X clock source, supporting systems running from 16 
    to 50 MHz 
o   Write back direct mapped, bank interleave cache 
    with size selections: 64, 128, 256, and 512K 
o   Supports 2-1-1-1, 3-1-1-1, 2-2-2-2
,   and 3-2-2-2 cache burst cycles 
o   Programmable cache and DRAM read/write cycles 
o   Built in TAG auto invalidation circuitry 
o   Programmable cache and DRAM read/write cycles 
o   Supports eight banks of 256K, 1 M, and 4M DRAMs for 
    configurations up to 64MB 
o   Supports 3-2-2-2 DRAM burst cycles 
o   Hidden refresh, slow refresh, and CAS before RAS refresh 
    supported 
o   Comprehensive VESA VL and OPTi high performance local bus 
    support 
o   Low power, high speed 0.8u CMOS technology 
o   Integrated peripherals controller 

**82C802         SCWB2 PC/AT Single Chip [no datasheet]              ?...
**82C802G/GP     System/Power Management Controller (cached)      c:93...
**82C895         System/Power Management Controller (cached)   c:Sep94...
**82C898         System/Power Management Controller (non-cache)c:Nov94...
**
**Support Chips:
**82C601/2       Buffer Devices                                 <Nov94...
**82C822         PCIB (VLB-to-PCI bridge)                         c:94...
**Other:...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...