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**?????  (Profusion)    c:99
Chips:         
Memory Access Controller (MAC)  
Data Interface Buffer (DIB)
CPUs:          8x P-III Xeon Oct
DRAM Types:    SDRAM PC100 2-way Interleave dual channel
Max Mem:       32GB
ECC/Parity:    ECC
AGP speed:     N/A
Bus Speed:     100
PCI Clock/Bus: 1/3 PCI-66/64



**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
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*OPTi...
**82C283         386SX System Controller                          c:91
***Notes:...
***Info:...
***Configurations:...
***Features:...
**82C291         SXWB PC/AT Chipset  (386SX)                      c:91...
**82C295         SLCWB PC/AT Chipset (386SX)                         ?...
**82C381/382     HiD/386             (386DX)                      c:89...
**82C391/392     386WB PC/AT Chipset (386DX)                    <Dec90...
**82C461/462     Notebook PC/AT chipset [no datasheet]               ?...
**82c463         SCNB Single Ship Notebook                        c:92...
**82c465MV/A/B   Single-Chip Mixed Voltage Notebook Solution    <Oct97...
**82C481?/482?   HiP/486 & HiB/486 [no datasheet]                Oct89...
**82C491/392     486WB PC/AT Chipset                         <04/21/91...
**82C493/392     486SXWB                                     <10/21/91...
**82C495SX/392SX LCWB PC/AT chipset [no datasheet]                   ?...
**82C495SLC      DXSLC 386/486 Low Cost Write Back                c:92...
**82C495XLC      PC/AT Chip Set                                   c:93...
**82c496A/B      DXBB PC/AT Chipset                             <Mar92...
**82C496/7       DXBB PC/AT Chipset (Cached)                 <01/16/92...
**82C498         DXWB PC/AT chipset [no datasheet]                   ?...
**82C499         DXSC DX System Controller                        c:93...
**82C546/547     Python PTM3V                                     c:94...
**82C556/7/8     Viper [no datasheet]                                ?...
**82C556/7/8N    Viper-N  Viper Notebook Chipset             <05/25/95...
**82C556M/7M/8E  Viper-N+ Viper Notebook Chipset                  c:96...
**82C566/7/8     Viper-Max Chipset Scalable MultiMedia PC Solution   ?...
**82C571/572     486/Pentium                                      c:93...
**82C576/7/8     Viper Xpress  [no datasheet]                        ?...
**82C576/8/9     Viper XPress+ [no datasheet, some info]     <01/16/97...
**82C596/597     PTMAWB Pentium Adaptive Write-back (Cobra)       c:93...
**82C650/1/2     Discovery (Pentium Pro) [no datasheet]              ?...
**82C681/2/6/7   386/486WB EISA                                   c:92...
**82C683         386/486AWB EISA [no datasheet]                      ?...
**82C693/6/7     Pentium uP Write Back Cache EISA                 c:93...
**82C700         FireStar                                         c:97...
**82C701         FireStar Plus                                    c:97
***Notes:...
***Info:
Overview
This section  describes the follow-on  chip to the OPTi  FireStar ACPI
solution, the FireStar Plus.  The key features of this new product can
be summarized as follows.

o   Mostly  backward-compatible in pin function and register set with 
    FireStar ACPI (some PIO functions have been moved from critical 
    pins to improve timing)
o   Implements ATA-33 (Ultra DMA) IDE Interface, with support for all 
    modes
o   Supports 2.5V CPUs
o   Incorporates MA13 support for 64Mb SDRAM chips
o   Incorporates 64Mb EDO DRAM support
o   Enables use of synchronous DRAM on all six banks (original 
    FireStar chip limited synchronous DRAM to the first four banks)
o   Allows redefinition of many interface pins for better utilization 
    of chipset PIO features (many new function pins are easily 
    available)

Features
The  following paragraphs  describe  the feature  set changes  between
FireStar ACPI and FireStar Plus.

Ultra DMA IDE Interface
The ATA33 specification for  synchronous bus mastering IDE, also known
as Ultra DMA, is fully supported by FireStar Plus.

Synchronous DRAM on All Banks 
The original FireStar chip  supports synchronous DRAM only on RAS0-3#.
FireStar  Plus  also  supports   synchronous  DRAM  on  RAS4-5#.   The
additional functionality  is selected  through register bits  that are
already defined on the FireStar ACPI part.

2.5V CPU Interface 
FireStar Plus supports newer CPUs with I/O voltage requirements as low
as 2.5V.  The pin redefinition is as follows.
o   Pins E8, G5, T5, and W5 are now VCC_CPU and can be powered at 2.5V 
    or 3.3V.  
o   Pins K5, H22, and AB19 are now VCC_CORE and must always be powered 
    at 3.3V.  
o   Pin M5, CPUCLKIN, must receive a clock on the VCC_CPU plane. So if 
    a 2.5V CPU is used, this clock should also be 2.5V.  

The 2.5V  interface is a strap-selected  option.  It is selected  by a
strap on pin B7 (new MA13 pin).  If B7 is sensed low at reset, the CPU
interface is  3.3V; if sensed high  along with TMS (pin  AB5) low, the
CPU interface is 2.5V.

Redefinition of DRQ/DACK# Interface
The 7  pins assigned  to DACK0-7# can  be redefined to  improve avail-
ability of PIO pins.

While the  new definition only  involves circuit modifications  to the
DACK0-7# pins,  the overall  gain is much  greater when used  with the
82C602A Companion Chip in its Viper Note-book Mode A configuration.

o   8 power management inputs are now available, muxed in with the 
    DRQs and IRQ8# on the four EPMMUX pins.  
o   7 full-featured PIO pins are available on the former FireStar 
    DRQ0-7 pins and IRQ8# pin. The number of pins is actually 8, but 
    is reduced b y 1 because one must be programmed as ATCLK/2.   
o   12 PPWR outputs are generated by latching the SD bus lines from 
    PCTLH (FireStar PPWRL) and PCTLL (FireStar RSTDRV).
o   The ISA bus RSTDRV signal is now generated by the 82C602A chip, so 
    that the FireStar RSTDRV pin can be used for PPWR generation 
    (power control latch control signal). If the extra PPWR signals 
    are not needed, the FireStar RSTDRV pin becomes useful as a full-
    featured PIO pin.

Warnings 
1.  Until the Extended Mode  option has been programmed, DACK3-7# will
be  driving out  against  the  signal input  muxes.   It is  therefore
important  to  ensure  that the  logic  will  not  be harmed  by  this
arrangement  (the  FireStar  outputs  safely accept  being  driven  by
external logic in this mode).

2.  EDACKEN is  an option used to ensure  proper ISA master operation.
It prevents the EDACK decoder  from glitching its DACK# outputs during
EDACK switching.  If ISA masters are not supported in the system, this
option is not needed (tie the EDACK line high on the 82C602A).

3.  There are  no provisions to block conflicts in  case more than one
pin is programmed to the same  function.  For example, if a PIO pin is
programmed to be  ACPI8-11, and the Extended Mode  option also enables
EPMMUX1 to bring in ACPI8-11, the results are unpredictable.

***Configurations:
82C701
82C701 + 82C602A

***Features:...
**82C750         Vendetta      [no datasheet]                        ?...
**82c801         SCWB2 DX Single Chip Solution                    c:92...
**82C802         SCWB2 PC/AT Single Chip [no datasheet]              ?...
**82C802G/GP     System/Power Management Controller (cached)      c:93...
**82C895         System/Power Management Controller (cached)   c:Sep94...
**82C898         System/Power Management Controller (non-cache)c:Nov94...
**
**Support Chips:
**82C601/2       Buffer Devices                                 <Nov94...
**82C822         PCIB (VLB-to-PCI bridge)                         c:94...
**Other:...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...

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