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**ET9000     "Jaguar" 486 Write Back Cache AT Single Chip       <Jun92
***Info:
The JAGUAR single chip provides high integration and low cost solution
for  a 16,  20, 25,  33  and 50MHz  486/AT based  system design.   Its
flexible architecture  allows Direct Mapped  Cache Implementation with
64KB/128KB/256KB/512KB  Cache.   The JAGUAR  combined  with 82C206  or
compatible peripheral controller offers a 100% PC/AT compatible system
using  less than  12 components  plus memory  devices.  The  ET9000 is
available in the 184-pin Plastic Quad Flatpack package.  The 1.0u high
speed, low power CMOS Technology allows for substantial stability when
running at 33 and 50MHz.

The JAGUAR  includes 486 CPU control,  write[back]-cache control, Page
Mode DRAM Control, a [local] DRAM control, AT Bus Control, Synchronous
AT Bus  Clock Generation, Clock  Switching Logic, data  bus conversion
logic which  performs the conversion  necessary between the 8,  16 and
32-bit  data paths.  A Coprocessor  Interface Logic  to  support Intel
487SX and Weitek 4167 are also included.

The  JAGUAR   ET9000  provides   very  flexible  cache   based  system
implementation  and a  Page Mode  DRAM memory  to  improve performance
during read  miss cycles.  System  performance is further  enhanced by
allowing  Refresh  and CPU  cache  hit  cycles  to occur  concurrently
without holding the CPU during Refresh cycle.

The system  cost is also minimized  by allowing the use  of slow SRAMs
and  DRAMs. The  "Write Back"  cache is  implemented to  minimize DRAM
access time during write cycle.

The JAGUAR is designed to be  100% compatible with the IBM PC/AT. With
its optimized Cache and DRAM design, enhanced features like Shadow RAM
BIOS, and  Concurrent Refresh; a high  performance / low  cost 486/ AT
can be implemented.

***Configurations:...
***Features:...
**ET9800/391 "Firefox" 386SX Write Back chipset [no datasheet]       ?...
**82C390SX   "Panda" S.C. 386SX Direct Mapped Cache [no d.sheet]cFeb92...
**66x8       VIA clones [no datasheet]                               ?...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**?????  (Profusion)    c:99
Chips:         
Memory Access Controller (MAC)  
Data Interface Buffer (DIB)
CPUs:          8x P-III Xeon Oct
DRAM Types:    SDRAM PC100 2-way Interleave dual channel
Max Mem:       32GB
ECC/Parity:    ECC
AGP speed:     N/A
Bus Speed:     100
PCI Clock/Bus: 1/3 PCI-66/64



**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
**82C571/572     486/Pentium                                      c:93
***Notes:...
***Info:...
***Configurations:...
***Features:...
**82C576/7/8     Viper Xpress  [no datasheet]                        ?...
**82C576/8/9     Viper XPress+ [no datasheet, some info]     <01/16/97...
**82C596/597     PTMAWB Pentium Adaptive Write-back (Cobra)       c:93...
**82C650/1/2     Discovery (Pentium Pro) [no datasheet]              ?...
**82C681/2/6/7   386/486WB EISA                                   c:92...
**82C683         386/486AWB EISA [no datasheet]                      ?...
**82C693/6/7     Pentium uP Write Back Cache EISA                 c:93...
**82C700         FireStar                                         c:97
***Info:...
***Configurations:...
***Features:...
**82C701         FireStar Plus                                    c:97...
**82C750         Vendetta      [no datasheet]                        ?...
**82c801         SCWB2 DX Single Chip Solution                    c:92...
**82C802         SCWB2 PC/AT Single Chip [no datasheet]              ?...
**82C802G/GP     System/Power Management Controller (cached)      c:93...
**82C895         System/Power Management Controller (cached)   c:Sep94...
**82C898         System/Power Management Controller (non-cache)c:Nov94...
**
**Support Chips:
**82C601/2       Buffer Devices                                 <Nov94...
**82C822         PCIB (VLB-to-PCI bridge)                         c:94...
**Other:...
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