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**Who made the first chip set?
By the  criteria of (2.)  in  'Definition of a chip  set' many sources
state this  to be the  Chips and Technologies  NEAT chip set.  I don't
know why this is stated as it is most definitely incorrect. The CS8221
NEW   Enhanced  AT   (NEAT)  chip   set  consisting   of  the   chips;
82C211/82C212/82C215/82C206  was  as far  as  I  can establish,  first
released sometime in 1986. 

C&T itself have an earlier chip set called the CS8220 PC/AT compatible
Chip  Set,  and  consists   of  the  following  chips;  82C201/82C202/
82A203/82A204/82A205.  It was  first  available  in OCT-85.  (see:C&T>
CS8220>Notes for further info.)

That is, AFAIK, the first motherboard  chip set from C&T and AFAIK the
worlds first chip set that meets the criteria of (2.). However C&T did
already have on the market their  popular EGA chip set, but that isn't
a motherboard chip set.

By the criteria of (1.), IBM, or Intel, see IBM>PC/XT chip set.

Another pre-'86 chipset is the  Faraday FE2010. The datasheet includes
a schematic on the very last  page dated 11/22/85. This only indicates
the chip set was on paper at that date. An acutal release date has not
been found.

**Spelling errors/mistyped words
Yes, I  know there are  spelling errors,  and things are  mistyped. It
seems no matter  how hard I try  my fingers hit 't'  twice when typing
'compatible' rendering it 'compattible' numerous, (thousands actually)
times.  I  don't have the  time or the will  to check the  spelling of
everything. Basic spell checking has been peformed. Please let me know
if  there is  anything that  would lead  to incorrect  information, or
something  is so  mangled  that  it needs  revising.  But  if you  can
basically  understand  what was  intended,  just  cope with  it.  Just
cope:-)

BTW, "110" port is  an "I/O" port that has been OCRed  badly, as is an
"1/0" port.

**Info needed on:...
**A note on VESA support of 486 chipsets....
**Datasheets:...
*_IBM...
*ACC Micro...
*ALD...
*ALi...
*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
*Contaq  . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82395SX     Smart Cache                                     12/17/90
***Notes:...
**82396SX     Smart Cache                                     12/17/90...
**82485       Turbo Cache (and 485Turbocache)                      c90...
**82489DX       Advanced Programmable Interrupt Controller    10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set                           <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
**82C898         System/Power Management Controller (non-cache)c:Nov94
***Notes:...
***Info:...
***Configurations:...
***Features:
o   Processor interface:
    - Intel 486SX, DX, DX2, SLe, DX4, P24T, P24D 
    - AMD 486DX, DX2, DXL, DXL2, Plus
    - Cyrix DX, DX2, M7
    - CPU frequencies supported 20, 25, 33, 40 and 50MHz
    - Auto clock detection
o   DRAM interface:
    - Up to 128MB main memory support
    - Supports 256KB, 1MB, 4MB, and 16MB single- and double-sided SIMM 
      modules
    - Read page-hit timing of 3-2-2-2 at 33MHz
    - Supports hidden, slow, and CAS-before-RAS refresh
    - Eight RAS lines to support eight banks of DRAM
    - Programmable wait states for DRAM reads and writes
    - Enhanced DRAM configuration map
    - Strong drive on MA lines (12/24mA)
    - Supports asymmetric DRAMs
o   Power management:
    - Support for SMM (System Management Mode) for system power
      management implementations
    - Programmable power management
    - Programmable wake-up events through hardware, software, and 
      external SMI source
    - Multiple level GREEN support (NESTED_GREEN)
    - STPCLK# protocol support
    - Programmable GREEN event timer
o   ISA interface:
    - 100% IBM PC/AT ISA compatible
    - Integrates DMA, timer, and interrupt controllers
    - Optional PS/2 style IRQ1 and IRQ12 latching
o   VESA VL interface:
    - Conforms to the VESA V2.0 specification
    - Optional support for up to two VL masters
o   Miscellaneous features:
    - Full support for shadow RAM, and write protection for video, 
      adapter, and system BIOS
    - Enhanced arbitration scheme
    - Transparent 8042 emulation for fast CPU Reset and Gate A20 
      generation
o   Packaging:
    - Higher integration
    - Reduced TTL count
    - Low-power, high-speed 0.8-micron CMOS technology
    - 208-pin PQFP (Plastic Quad Flat Pack)

**
**Support Chips:
**82C601/2       Buffer Devices                                 <Nov94...
**82C822         PCIB (VLB-to-PCI bridge)                         c:94...
**Other:...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...