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**Who made the first chip set?
By the criteria of (2.) in 'Definition of a chip set' many sources
state this to be the Chips and Technologies NEAT chip set. I don't
know why this is stated as it is most definitely incorrect. The CS8221
NEW Enhanced AT (NEAT) chip set consisting of the chips;
82C211/82C212/82C215/82C206 was as far as I can establish, first
released sometime in 1986.
C&T itself have an earlier chip set called the CS8220 PC/AT compatible
Chip Set, and consists of the following chips; 82C201/82C202/
82A203/82A204/82A205. It was first available in OCT-85. (see:C&T>
CS8220>Notes for further info.)
That is, AFAIK, the first motherboard chip set from C&T and AFAIK the
worlds first chip set that meets the criteria of (2.). However C&T did
already have on the market their popular EGA chip set, but that isn't
a motherboard chip set.
By the criteria of (1.), IBM, or Intel, see IBM>PC/XT chip set.
Another pre-'86 chipset is the Faraday FE2010. The datasheet includes
a schematic on the very last page dated 11/22/85. This only indicates
the chip set was on paper at that date. An acutal release date has not
been found.
**Spelling errors/mistyped words...
**Info needed on:...
**A note on VESA support of 486 chipsets....
**Datasheets:...
*_IBM...
*ACC Micro...
*ALD...
*ALi...
*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
*Contaq . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**????? (Profusion) c:99
Chips:
Memory Access Controller (MAC)
Data Interface Buffer (DIB)
CPUs: 8x P-III Xeon Oct
DRAM Types: SDRAM PC100 2-way Interleave dual channel
Max Mem: 32GB
ECC/Parity: ECC
AGP speed: N/A
Bus Speed: 100
PCI Clock/Bus: 1/3 PCI-66/64
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
**SL9350 Page Mode Memory Controller (16/20/25MHz 16MB Max) <oct88
***Info:...
***Versions:...
***Features:
o 16, 20, 25 MHz Options.
o Enhanced fast page mode design.
o Programmable wait state options.
o Shadow Ram feature.
o Supports 16 M byte of on board memory.
o Can use 256K x 1, 1 Meg x 1, and 256K x 4 DRAMs or a mix.
o Supports 100 ns DRAMs at 16 MHz and 80 ns at 20 MHz.
o Automatic remapping of 640K - 1 M RAM to top of the address space.
o Advance CMOS Technology.
o 100 pin Flatpack.
.
**Other:...
*Motorola...
*OPTi...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...
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