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**M1521/23       Aladdin III       50-66MHz                     <Nov96
***Info:...
***Configurations:...
***Features:
****M1521 System Controller:
o   Supports all Intel/Cyrix/AMD/TI 586-class processors. Host bus at 
    66 MHz, 60 MHz and 50MHz at 3.3V.
    - Supports linear wrap mode for M1
o   Supports Async/Pipelined-Burst SRAM
    - Direct mapped, 256KB/512KB/1MB
    - Write-Back/Dynamic-Write-Back cache policy
    - Built-in 8K*2 bit SRAM for MESI protocol to reduce cost and 
      enhance performance
    - Cacheable memory up to 64MB with 8-bit Tag SRAM
    - Cacheable memory up to 512MB with 11-bit Tag SRAM
    - 3-1-1-1-1-1-1-1 for Pipelined Burst SRAM at back-to-back burst 
      read and write cycles.
    - Supports 3V/5V SRAMs for Tag Address
o   Supports FPM/EDO/BEDO/SDRAM DRAMs
    - 8 RAS Lines
    - 64-bit data path to Memory
    - Symmetrical/Asymmetrical DRAMs
    - 3.3V or 5V DRAMs
    - Duplicated MA[1:0] driving pins for burst access
    - No buffer needed for RASJ and CASJ and MA[1:0]
    - CBR and RAS-only refresh
    - 8 QWORD deep merging buffer for 3-1-1-1-1-1-1-1 posted write 
      cycle
    - 6-3-3-3-3-3-3-3 for back-to-back FPM read-page-hit (@ 66mhz)
      5-2-2-2-2-2-2-2 for back-to-back EDO read-page-hit (@ 66mhz)
      6-1-1-1-1-1-1-1 for back-to-back BEDO read-pagehit (@ 66mhz)
      7-1-1-1-2-1-1-1 for back-to-back SDRAM readpage-hit (@ 66mhz)
      4-2-2-2-2-2-2-2 for back-to-back EDO read-page-hit (@ 60mhz)
      5-1-1-1-1-1-1-1 for back-to-back BEDO read-pagehit (@ 60mhz)
      2-2-2-2 for retired data for posted write on FPM and EDO page-
      hit
      x-1-1-1 for retired data for posted write on BEDO and SDRAM 
      page-hit
    - Supports 64M-bit (16M*4, 8M*8, 4M*16) technology DRAMs
    - Supports Programmable-strength RAS/CAS/MWE/MA buffers.
    - Supports Error Checking & Correction (ECC) and Parity for DRAM
    - Supports the most flexible six 32-bit populated banks of DRAM 
      (to spare 12MB for Windows 95)
    - Supports SIMM and DIMM
o   UMA (Unified Memory Architecture)
    - Dedicated UMA Arbiter Pins
    - Supports several protocols from major graphics vendors.
    - SFB size : 512KB/1MB/2MB/3MB/4MB
    - CPU could access frame buffer memory through system memory 
      controller
    - Alias address for frame buffer memory
o   Fully synchronous 25/30/33Mhz 5V PCI interface
    - PCI bus arbiter: five PCI masters and M1523 (ISA Bridge) 
      supported
    - 5 DWORDs for CPU-to-PCI Memory write posted buffers
    - Convert back-to-back CPU to PCI memory write to PCI burst cycle
    - 22 DWORDS for PCI-to-DRAM Write-posted/ Readprefetching buffers
    - PCI-to-DRAM up to 133 MB/sec bandwidth (even when L1/L2 write-
      back)
    - L1/L2 pipelined snoop ahead for PCI-to-DRAM cycle
    - Supports PCI mechanism #1 only
    - PCI spec. 2.1 support. (N(16/8)+8 rule, passive release, fair 
      arbitration)
    - Enhanced performance for Memory-Read-Line and Memory-Read-
      Multiple and Memory-write-Invalidate PCI commands.
o   DRAM refresh during 5V system Suspend
o   I/O leakage stopper for power saving during system suspend.
o   328-pin or 388-pin BGA process

****M1523 PCI-to-ISA Bridge:...
**M1531/33/43    Aladdin IV & IV+  50-83.3MHz                <05/28/97...
**M1541/42/33/43 Aladdin V & V+    50-100MHz                         ?...
**M1561/43/35D   Aladdin 7 ArtX    [no datasheet, some info]  11/08/99...
**M6117          386SX Single Chip PC                              <97...
**
**Support Chips:
**M1535/D        South Bridge                                        ?...
**
**May not exist:...
**Later Chipsets:...
**Other:...
*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
*Contaq  . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82395SX     Smart Cache                                     12/17/90
***Notes:...
**82396SX     Smart Cache                                     12/17/90...
**82485       Turbo Cache (and 485Turbocache)                      c90...
**82489DX       Advanced Programmable Interrupt Controller    10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set                           <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
**800 series...
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