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M2228 	Video
M2301 	Video
M2302 	Video
M2308 	Video
M2401 	Video
M3125 	Video
M3135 	Video (super VGA)
M3143 	Video
M3145 	PCI Video
M3145 	VLB/PCI 3D Video
M3147V 	PCI Video
M3149 	Video
M3151 	PCI 3D Video, 4MB MAX
M3307   MPEG    Video Decoder Chip
M3309   MPEG-II Video Decoder Chip
M3321   MPEG-II A/V Decoder Chip
M3351   MPEG-II Video Decoder Chip
M4803 	PCI EIDE Controller
M5105 	VLB Super I/O Controller FDD/HDD/LPT/2xCOM/GAME	 
M5113   Superset of 5105, with PnP, ECP/EPP LPT and IR port
M5119 	Super I/O
M5123 	Super I/O   PnP/2xCOM/IR port/Keyboard (For Phoenix BIOS)
M5125 	same as  M5123 but for AMI
M513? 	Super I/O PnP/Keyboard
M5135F 	Super I/O PnP/Keyboard/IR
M514? 	Super I/O PnP/Keyboard/IR/2xCOM/  
M5213 	PCI IDE
M5217/H	Super I/O
M5219 	PCI? Bus mastering EIDE
M5225 	PCI? EIDE
M5229 	PCI? Bus mastering EIDE
M5235 	Super I/O
M5237 	PCI USB Host
M5240 	PCI? EIDE
M5241 	PCMCIA Bridge
M5242 	? 
M5244 	FDD
M5427 	PCI-AGP Bridge
M5451 	Audio 
M5453 	Modem 
M5455 	Audio  

*AMD . . . . . . . [no datasheets, some info]...
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**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93
***Notes:...
***Info:...
***Configurations:...
***Features:...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
**800 series...
*Headland/G2...
**HT35          Single-Chip Peripheral Controller [partial info]     ?
***Notes:...
**HTK320        386DX Chip Set                                 c:Sep91...
**HTK340        "Shasta" 486 Chip Set                          c:Jun92...
**Support Chips:
**HT44          Secondary Cache                                c:Jun92
***Info:
The  HT44 is  a  look-aside write-through,  80486SX,  486DX or  486DX2
secondary cache  controller. It is  packaged in an  inexpensive 84-pin
plastic-leaded chip carrier (PLCC).

Architecture
With  its look-aside architecture,  the HT44  fits beside  the CPU-to-
Memory bus  and not in  the data path.   Therefore, once the  HT44 has
been designed  into a  486 system, it  can be populated  for secondary
cache systems or left vacant for non-secondary cache systems. The HT44
is direct-mapped to the available address space.

Performance
The  HT44  has a  number  of  performance  enhancing features.   These
include zero-waitstate burst line fills  to the 486 on secondary cache
hits, and simultaneous 486 and secondary cache updates on read misses.

Memory Configurations
The HT44 supports  cache sizes from 32KBytes to  1MB. Both synchronous
and asynchronous  SRAMs are supported.  25ns SRAMs are  sufficient for
zero-wait-state operation at 33MHz.

Chip Set Support
The HT44 can,  be implemented with minimal glue logic  in a 486 system
with the  HTK340 (code  name Shasta) chip  set.  The registers  in the
HTK340  allow  for programming  of  non-cacheable and  write-protected
areas of  memory. The  HTK340 will support  the HT44  with synchronous
SRAMs only.   Future Headland chip sets will  support both synchronous
and asynchronous SRAM designs.

The HT44  can also be used  with some third-party  chip sets, however,
additional glue logic may be required.

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