[Home] [This version is outdated, a new version is here]
*Title...
*Search:...
*Read Me/FAQ/General Info...
*_IBM...
*ACC Micro...
*ALD...
*ALi...
*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
*Contaq  . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82485       Turbo Cache (and 485Turbocache)                      c90
***Notes:...
***Info:
The 82485 is  a second-level cache controller designed  to improve the
performance  of  Intel486  Microprocessor  systems.  One  82485  cache
controller supports  64K or  128K bytes of  second level  cache memory
that maps  to the  entire 4 Gigabytes  of the  Intel486 microprocessor
address space. The controller  is completely software transparent. One
controller plus SRAMs  provides a 64K or a  128K cache. External EPROM
can  be  cached  yet  remain  write protected.   The  82485  is  fully
compatible  with the  Intel486  microprocessor. All  Intel486 CPU  bus
cycles and timings are supported.

A complete, optional second level  cache controller using the 82485 is
available  as the 485Turbocache  Module from  Intel (data  sheet order
number 240722).

2.0 FUNCTIONAL DESCRIPTION
2.1 Introduction
The 82485 is a single ported, two-way set associative cache controller
designed specifically  to interface with  the Intel486 microprocessor.
The controller supports either a sectored configuration (two lines per
tag) or  a non-sectored configuration  (one line per tag).   The 82485
will directly support a nonsectored  64K data cache or a 128K sectored
data cache.  Both the 64K and  128K configurations are able to map the
entire 4 gigabytes of  the Intel486 microprocessor address space.  The
82485 interfaces directly to  the Intel486 microprocessor.  All Intel-
486 CPU bus cycles and timings are supported.  The 82485 also supports
0 wait  state processor operation  when there is  a cache hit  and has
provisions to support invalidation cycles, BOFF# cycles, and premature
BLAST# terminations.  The controller  is look aside (monitors bus act-
ivity in parallel to the processor) and write through (all writes pro-
pagate to the  system bus), so it supports  the same cache consistency
mechanisms as the  Intel486 CPU.  The controller also  provides a safe
method to cache ROM BIOS through the  use of a write protect pin and a
write protect strapping option.

The data cache  (Static RAM) resides external to  the 82485. The 82485
provides all  controls for  the SRAMs.  No  external latches  or tran-
ceivers are  required.  The 82485  output buffers support up  to eight
SRAMs.  A  64K cache can be  designed with only  five components; nine
components for a 128K cache.  Two-way set associativity is provided by
dual banked SRAMs. Data parity is supported.

The  82485  can  be  used  to  design  a  custom  second  level  cache
configuration. For an easier system design and higher integration, the
82485M Turbocache  can be used  (see data sheet order  number 240722).
This  module is  a  complete second  level  cache in  one package.  It
consists  of a single  82485 cache  controller and  SRAM to  provide a
complete 64K or 128K second level Intel486 microprocessor second level
cache.

***Versions:...
***Features:...
**82489DX       Advanced Programmable Interrupt Controller    10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set                           <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99
Chips:         
Memory Access Controller (MAC)  
Data Interface Buffer (DIB)
CPUs:          8x P-III Xeon Oct
DRAM Types:    SDRAM PC100 2-way Interleave dual channel
Max Mem:       32GB
ECC/Parity:    ECC
AGP speed:     N/A
Bus Speed:     100
PCI Clock/Bus: 1/3 PCI-66/64



**800 series...
*Headland/G2...
**HT21          386SX/286 Single Chip (20 MHz)                 c:Aug91
***Info:
The HT21  is an  advanced PC/AT compatible,  single-chip 80386SX/80286
design solution.   This highly  integrated single chip  allows simple,
low cost  system design options while featuring  high performance, low
power  consumption,  and minimum  board  space requirements.  Advanced
memory management features  include support for page mode,  2 or 4-way
interleaving in  both pipelined and  non-pipelined modes. The  LIM 4.0
hardware implementation  features dual sets of 32  registers with full
context support for highest performance Optimization of extended local
memory  accesses. An  advanced  EMS hardware  write-protect option  is
provided. The HT21 supports 256K and 1M DRAMs in l by 1, 1 by 4, and 1
by 9 device configurations for up  to 8MB of on-board system memory. A
flexible Shadow  RAM option for  System and Video  BIOS as well  as 8-
16-bit BIOS Options adds to overall design versatility.

A  complete PC/AT  compatible  system with  advanced  features may  be
implemented with minimal external support logic. The HT21 performs all
CPU  and peripheral support  functions in  a single  chip.  Integrated
device  functions include  DMA Controllers,  a Memory  Mapper, Timers,
Counters, Interrupt  Controllers, a Bus Controller  and all supporting
circuitry for PC  core logic requirements. The chip  also contains all
the  necessary  address buffers,  data  transceivers, memory  drivers,
parity  checking   and  supporting  circuitry  for   a  complete  high
performance computer solution. An asynchronous AT Bus clock allows for
a constant 8MHz Bus clock rate for highest bus device compatibility as
defined in  IEEE Spec P996.   In controlled bus applications  the HT21
supports up to a  12 MHz Bus Clock rate. This device  is packaged in a
208-pin Plastic Quad Flat Pack combining several external buffers into
this space saving solution.

***Configurations:...
***Features:...
**HT22          386SX/286 Single Chip (25 MHz)                 c:Sep91...
**HT25          3-volt Core Logic for 386SX                    c:Dec92...
**HT35          Single-Chip Peripheral Controller [partial info]     ?...
**HTK320        386DX Chip Set                                 c:Sep91...
**HTK340        "Shasta" 486 Chip Set                          c:Jun92...
**Support Chips:
**HT44          Secondary Cache                                c:Jun92...
**Other:...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...

(c) Copyright mR_Slugs Warehouse - All rights Reserved