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**82485 Turbo Cache (and 485Turbocache) c90
***Notes:...
***Info:...
***Versions:...
***Features:...
**82489DX Advanced Programmable Interrupt Controller 10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93
***Notes:...
***Info:...
***Configurations:...
***Features:
o High Performance Second Level Cache
- Zero Walt States at 66 MHz
- Two-way Set Associative
- Write-Back with MESI Protocol
- Concurrent CPU Bus and Memory Bus Operation
- Boundary Scan
o Pentium Processor
- Chip Set Version of Pentium Processor
- Superscalar Architecture
- Enhanced Floating Point
- On-chip SK Code and SK Data Caches
- See Pentium Processor User's Manual Volume 2 for more
Information
o Highly Flexible
- 256K to 512K with parity
- 32, 64, or 128-Bit Wide Memory Bus
- Synchronous, Asynchronous, and Strobed Memory Bus Operation
- Selectable Bus Widths, Line Sizes, Transfers, and Burst Orders
o Full Multiprocessing Support
- Concurrent CPU, Memory Bus, and Snoop Operations
- Complete MESI Protocol
- Internal/External Parity Generation/Checking
- Supports Read-for Ownership, Write-Allocation, and Cache-to-
Cache Transfers
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99
Chips:
Memory Access Controller (MAC)
Data Interface Buffer (DIB)
CPUs: 8x P-III Xeon Oct
DRAM Types: SDRAM PC100 2-way Interleave dual channel
Max Mem: 32GB
ECC/Parity: ECC
AGP speed: N/A
Bus Speed: 100
PCI Clock/Bus: 1/3 PCI-66/64
**800 series...
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