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**82C596/A  3/486 Writeback Cache [no datasheet]             <11/11/92
Possibly  two variant,  or one  version with  two names,  one  being a
shorthand:
82C596
82C596A

ftp://ami.com/archive/Other_Manuals/!index.txt
lists the A variant with the date 11/11/92. No date for non-A:
" 
CTQ596.Z06    	88900   12-21-92  3/486 Contaq 596 chipset    06-06 core  
CTQ596A.Z11   	95383   10-07-93  3/486 Contaq 596-A for 11/11/92  
CTQ596_3.Z06   	92195   03-01-93  386   Contaq 596  
CTQ596_3.Z11    98031  	06-21-93  386   Contaq 596
CTQ596_4.Z06    92236  	03-01-93  486   Contaq 596
CTQ596_4.Z11    97602  	06-21-93  486   Contaq 596
CT596A.Z08   	96217   12-09-93  Contaq 596a  
"
Note, the column of dates is the file date.

**??????    486 EISA chipset [no datasheet]                     <Feb93...
**82C599    PCI-VLB Bridge [no datasheet, some info]                 ?...
**82C693    PCI-ISA Bridge [no datasheet]                            ?...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91
***Notes:...
***Info:...
***Features:
o   Two-Way, Set Associative, Secondary Cache for i860 XP 
    Microprocessor
o   50 MHz "No Glue" Interface with CPU
o   Configurable
    - Cache Size 256 or 512 Kbytes
    - Line Width 32, 64 or 128 Bytes
    - Memory Bus Width 64 or 128 Bits
o   Dual-Ported Structure Permits Simultaneous Operations on CPU and
    Memory Buses
o   Efficient MRU Way Prediction
    - Zero Wait States on MRU Hit
    - One Walt State on MRU Miss
o   Dynamically Selectable Update Policies
    - Write-Through
    - Write-Once
    - Write-Back
o   MESI Cache Consistency Protocol
o   Hardware Cache Snooping
o   Maintains Consistency with Primary Cache via Inclusion Principle
o   Flexible User-Implemented Memory Interface Enables Wide Range of
    Product Differentiation
    - Clocked or Strobed
    - Synchronous or Asynchronous
    - Plpelining
    - Memory Bus Protocol
o   82495XP Cache Controller Available in 208-Lead Ceramic Pin Grid 
    Array Package
o   82490XP Cache RAM Available in 84-Lead Plastic Quad Flatpack 
    Package

**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:
Chips:
[82454NX] (PXB) [82453NX] (MUX) 
[82452NX] (RCG) [82451NX] (MIOC) 
[82371EB] (PIIX4E),                            
CPUs:          Single/Dual/Quad P-II Xeon/P-III Xeon
DRAM Types:    FPM EDO 2-way Interleave 4-way Interleave
Mem Rows:      8
DRAM Density:  16Mbit 64Mbit
Max Mem:       8GB
ECC/Parity:    Both
AGP speed:     N/A
Bus Speed:     100
PCI Clock/Bus: 1/3


**?????  (Profusion)    c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
**SL6012  Memory Mapper for PC-AT (74LS612 compatible)          <Jul87
***Info:...
***Versions:...
***Features:...
**SL9010  System Controller (80286/80386SX/DX, 16/20/25MHz)     <oct88...
**SL9020  Data Controller                                       <oct88...
**SL9025  Address Controller                                    <oct88...
**SL9090  Universal PC/AT Clock Chip                            <oct88...
**SL9250  Page Mode Memory Controller (16/20MHz 8MB Max)        <oct88...
**SL9350  Page Mode Memory Controller (16/20/25MHz 16MB Max)    <oct88...
**Other:...
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*Unresearched:...
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*General Sources:...