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*_IBM...
*ACC Micro...
**ACC2046/ST 486DX/486SX/386DX Single Chip AT                   <Jul92
***Info:...
***Configurations:...
***Features:
o   100% IBM PC/AT compatible
o   Supports 486DX up to 50 Mhz
o   Supports 4868X and 487SX
o   Supports Intel Low Power 486DX/SX
o   Supports 386DX up to 40 MHz
o   Supports 387 and Weitek 4167/3167 numerical coprocessors
o   Supports 1x or 2x system clock
o   Integrated flexible direct mapped cache controller for up to 
    2048KB
o   Supports posted write or write-through cache operation
o   Supports 3 programmable non-cacheable ranges
o   Supports 64 MB DMA address space
o   Supports one to four memory banks of 32 bit DRAM using 256K, 1M or
    4M DRAMs allowing 64 Mbytes on system board.
o   Operates with page mode or two/four way page interleaved mode
o   Programmable DRAM timing parameters
o   Programmable slow refresh
o   Supports hidden refresh
o   Support Dynamic Memory remapping
o   Unused RAS and CAS lines can be disabled
o   Supports shadow RAM for video and system BIOS
o   Supports 8 or 16 bit wide BIOS ROMs in 128K or 64K EPROM space
o   Supports single ROM
o   Supports 512K ROM size
o   Middle BIOS can be disabled
o   Bus "quiet" mode assures that slot bus signal lines are driven 
    only during slot accesses
o   Port 8 and NMI logic
o   Internal switching and programmable CLK2 for sleep mode Operation 
    (can be divided by 2/4/8/16)
o   Fast reset / Fast gate A20 (Port 92)
o   Support for PC/AT compatible and turbo modes
o   Independent ISA Bus control
o   Parity generation and detection logic
o   Integrated Peripheral Functions: 2x 8237, 2x 8259, 1x 8254.
o   Bus conversion between D,SD and XD
o   Data latches and buffers included
o   208-pin PQFP device

**ACC2048    WB 486 Notebook/Embedded Single Chip [no datasheet]     ?...
**ACC2051/NT PCI Single Chip Solution for Notebook Applications    c96...
**ACC2056    ?Pentium 3.3V Notebook               [no datasheet]<Jan96...
**ACC2057    PCI Notebook/Embedded Single Chip    [no datasheet]<Aug96...
**ACC2066NT  486 Notebook/Embedded Single Chip    [no datasheet]     ?...
**ACC2086    486 VL-based System Super Chip Soluti[no datasheet]     ?...
**ACC2087    Enhanced Super Chip (486 Single Chip)              <Aug96...
**ACC2089    486 PCI-based System Super Chip      [no datasheet]     ?...
**ACC2168/GT 32-bit 486 Green System Single Chip  [no datasheet]     ?...
**ACC2178A   32-bit 486 Green System Single Chip  [no datasheet]     ?...
**ACC2268    ?486                                 [no datasheet]     ?...
**ACC????    Maple/Maple-133 486-System-On-Chip   [no datasheet]     ?...
**
**Support Chips:
**ACC2016    Buffer and MUX Logic                                  c96...
**ACC2020    Power Management Chip                                 c92...
**ACC5500    Multifunction I/O Control Chip for PS2 Model 50/60    c88...
**
**Other chips...
*ALD...
*ALi...
*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
*Contaq  . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82395SX     Smart Cache                                     12/17/90
***Notes:...
**82396SX     Smart Cache                                     12/17/90...
**82485       Turbo Cache (and 485Turbocache)                      c90...
**82489DX       Advanced Programmable Interrupt Controller    10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set                           <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94
***Notes:...
***Info:
The 82498 Cache Controller and multiple 82493 Cache SRAMs combine with
the Pentium processor (735/90,  815/100) and future Pentium Processors
to form a CPU Cache chip set designed for high performance servers and
function-rich  desktops. The high-speed  interconnect between  the CPU
and  cache components has  been optimized  to provide  zero-wait state
operation. This CPU  Cache chip set is fully  compatible with existing
software,  and has new  data integrity  features for  mission critical
applications.

The 82498 Cache Controller implements the MESI write-back protocol for
full multiprocessing support.  Dual ported buffers and registers allow
the 82498  to concurrently  handle CPU bus,  memory bus,  and internal
cache operation for maximum performance.

The 82493 is a customized high-performance SRAM that supports 64-, and
128-bit  wide memory  bus widths,  32-,  and 64-byte  line sizes,  and
optional sectoring. The  data path between the CPU  bus and memory bus
is  separated  by  the  82493,  allowing  the  CPU  bus  to  handshake
synchronously,  asynchronously,  or   with  a  strobed  protocol,  and
allowing concurrent CPU bus and memory bus operations.

***Configurations:...
***Features:...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
**800 series...
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