mR_Slug's Warehouse > Chipset Encyclopedia:

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**82489DX Advanced Programmable Interrupt Controller 10/12/92
***Notes:...
***Info:...
***Versions:...
***Features:...
**82495DX/490DX DX CPU-Cache Chip Set <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91
***Notes:...
***Info:...
***Features:...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
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**450NX (?) 06/29/98:...
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**82C281/282 Cache Sx/AT (386SX) <08/22/91
***Notes:...
***Info:...
***Configurations:...
***Features:
o Flexible DRAM Banks Configuration
- The 82C281/2 supports 256K, 1M, and 4M memory devices, total
main memory size can be up to 16MB. A total of 12 different
memory configurations are supported.
o Page Mode Operation
- Based on the memory configuration shown above [see datasheet],
the memory control unit inside the 820281/2 performs page mode
of operation with a varying block size of 1k, 2k, or 4k bytes
for 256k, 1M, or 4M DRAMs respectively.
o System BIOS Shadow RAM
- The 820281/2 memory control unit provides shadow RAM feature for
several areas of memory system BIOS, video BIOS, and adapter
BIOS.
o Memory Remapping
- If shadow RAM feature is not utilized for the memory area
between 0D0000H - 0EFFFFH, then memory remapping is possible.
The local DRAM areas, 0A0000H - 0BFFFFH and 0D0000H - 0EFFFFH, a
total of 256 KByte, are remapped to the top of total system
memory. The areas for 0F0000H-0FFFFFH (system BIOS) and
0C000H-0CFFFFH (Video BIOS) are reserved for shadow RAM purpose.
o Flexible Multiplexed DRAM Address
o Cache Control Subsystem
- Direct-mapped posted write cache control function provides a low
cost alternative to enhance the system performance by up to 50%.
In order to simplify the design without increasing the system
cost or decreasing performance, the 82C281/2 has been designed
to support only non-pipeline mode for systems with cache memory.
The 82C281/2 offers the following cache control features:
- Flexible Cache Memory Size
- 4MB Cacheabie main memory by using 16KB low cost SRAM.
- 8MB Cacheable main memory by using 32KB low cost SRAM.
- Cache 16MB main memory by using 64KB low cost SRAM.
- Increase the cache size beyond 64KB up to 512KB
- Cache Line Size 4 Byte
- Burst mode memory prefetch is supported by the 82C281/2.
During cache read miss cycles, the memory control subsystem
will perform two consecutive read cycles to fetch 4 bytes
from main memory before terminating the cycle by sending
RDYO# signal to 3868X.
- Non-Cacheable Area
The non-cacheable areas are predefined as indicated below:
- I/O address space
- memory address between 0A0000H and 0FFFFFH.
- any memory address beyond the current configured memory
size.
- programmable non-cacheable memory area as defined by
82C281/2 internal registers.
- 82C281 Posted Write Cache
- The 820281 supports flexible direct-mapped cache with posted
write through update of main memory. By programming the
internal register, the post write control signals are
provided by the 820281 to support a one level write buffer.
With posted write, the CPU write cycles can be completed in
2 CPU T-States, thereby increasing system performance.
- 820282 Write Through Cache
- The 820282 supports a write-through cache system which
allows the designer to reduce system cost by eliminating two
F244's and two F373‘s with only a slight reduction in system
performance (5-10%).
- AT Bus Control
- The 820281/2 AT bus control unit handles all of the AT bus
operations and the DMA/Refresh arbitration. The AT bus
control unit supports the following features:
- Programmable AT Bus Clock - The AT bus clock, ATCLK. can
be programmed as CLK2/6, which is default, or CLK2/4.
- Turbo Switch - The 820281/2 provides a turbo switch
feature that allows users to change the system clock
speed. A programmable bit will enable or disable this
turbo function. When the turbo function is enabled by
setting reg[14H], bit[1] to 1, the 82C281/2 turbo pin
then determines the system clock speed. A low on the
turbo pin forces the CPU to run at the current AT bus
speed which IS CLK2/6 or CLK2/4.

IMAGING DEVICES
ICS90C61A Dual Video/Memory Clock Generator
ICS90C63 Dual Video/Memory Clock Generator
ICS90C64 Dual Video/Memory Clock Generator
WD90C00 VGA Controller (8514/A clone, max 1MB, 1024x768x16, 800x600x256)
WD90C01 8514/A for laptops
WD90C10 VGA, 256KB
WD90C11, WD90C11A Enhanced VGA Controller (max 512KB, 1024x768x16, 800x600x256)
WD90C20, WD90C20A VGA Flat Panel Display Controller (800x600x16, 640x460x256, 32 shades gray)
WD90C22 VGA Flat Panel Display Controller (800x600x16, 640x460x256, 64 shades gray)
WD90C24/A/A2 SVGA, max 1MB, 1280x1024x16, 1024x768x16, LCD, VESA-LB, 3.3 or 5V
WD90C26 VGA Flat Panel Display Controller
WD90C30 High Performance Video Controller (max 1MB, 1024x768x256, 1024x768x16)
WD90C31 Accelerator Video Controller (max 1MB, 1024x768x256, 1280x1024x16)
WD90C33 Same as WD90C31 but with, max 2MB, VESA-LB, 1280x1024x256, 1280x1024x16)
WD90C55 VGA LCD Interface
WD90C56 VLBI (Video Local Bus Interface), for WD90C30/31, VESA not mentioned.
WD9710 Pipelined, 32bit core, 64bit RAM, 24bit RAMDAC, PCI/VLB
WD9712 similar to WD9710

STORAGE DEVICES
WD10C01A Winchester Disk Controller
WD10C27 Data Separator
WD33C92A Enhanced SCSI Bus Interface Controller
WD33C93B Enhanced SCSI Bus Interface Controller
WD33C95A, WD33C96A Enhanced Single-ended and Differential SCSI Bus Interface Controller
WD37C65C Floppy Disk Subsystem Controller Device
WD42C22C Winchester Disk Subsystem Controller Device
WD60C318 Optical Disk Drive Encoder/Decoder
WD60C40A Peripheral Cache Manager Device
WD60C80 Error Detection and Correction Chip (EDAC)
WD61C23A High Performance Hard Disk Controller
WD61C40A Peripheral Cache Manager Device
WD7000 ESDI Controller (16-bit ISA)
WD7193 Fast SCSI-II PCI adapter, 33C296A-ZX chip
WD7197 Fast Wide version of WD7193
WD7296A Fast Wide SCSI-II (PCI?), possibly WD34C296 chip

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