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*ACC Micro...
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ACC1200 Clock synthesizer Supports Pentium-Pro and Pentium-class PCI
ACC16C451 Multi I/O 1x16450/1xLPT
ACC16C452 Multi I/O 2x16450/1xLPT
ACC16C461 Multi I/O 1x16450/1xLPT
ACC2042 Keyboard/Mouse Controller
ACC2188 PCI bus controller Support 32-bit PCI Bus interface with built-in power management control and synchronous / asynchronous clock feature.
ACC3201 PC/XT/AT FDD Controller
ACC3202 PS/2 FDD Controller
ACC3203 PS/2 FDD Controller
ACC3211 PC AT/XT FDD Controller (x4) + with IDE
ACC3221 Multi I/O Controller, floppy/IDE/2x16450/1xLPT
ACC3223 Multi I/O Controller, floppy/IDE/2x16550/1xLPT
ACC3350 Ultra SCSI
ACC3360 UltraWide SCSI
ACC3618 3D surround controller ISA
ACC5810 Micro Channel Interface Chip
ACC808 Plug-and-Play Controller
ACC???? Manhattan PCI-based FireWire for Pentium
ACC???? Memphis PCI-based CardBus and FireWire
*ALD...
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*AMD . . . . . . . [no datasheets, some info]...
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*Contaq . . . . . [no datasheets, some info]...
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*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82395SX Smart Cache 12/17/90
***Notes:...
**82396SX Smart Cache 12/17/90...
**82485 Turbo Cache (and 485Turbocache) c90...
**82489DX Advanced Programmable Interrupt Controller 10/12/92
***Notes:...
***Info:
1.0 INTRODUCTION
The 82489DX Advanced Programmable Interrupt Controller provides
multiprocessor interrupt management, providing both static and dynamic
symmetrical interrupt distribution across all processors.
The main function of the 82489DX is to provide interrupt management
across all processors. This dynamic interrupt distribution includes
routing of the interrupt to the lowest-priority processor. The 82489DX
works in systems with multiple I/O subsystems, where each subsystem
can have its own set of interrupts. This chip also provides
inter-processor interrupts, allowing any processor to interrupt any
processor or set of processor. Each 82489DX I/O init interrupt input
pin is individually programmable by software as either edge or level
triggered. The interrupt vector and interrupt steering information an
be specified per pin. A 32-bit wide timer is provided that can be
programmed to interrupt the local processor. the timer can be used as
a counter to provide a time base to software running on the processor,
or to generate time slice interrupts locally to that processor. the
82489DX provides 32-bit software access to its internal
registers. Since no 82489DX register read have any side effects, the
82489DX registers can be aliased to a user read-only page for fast
user access (e.g., performance monitoring timers).
The 82489DX supports a generalized naming/addressing scheme that can
be tailored by software to fit a variety of system architectures and
usage models. It also supports 8259A compatibility by becoming
virtually transparent with regard to an externally connected 8259A
style controller, making the 8259A visible to software.
***Versions:...
***Features:...
**82495DX/490DX DX CPU-Cache Chip Set <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
**800 series...
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