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**Why this document is not GPL or a wiki
The document is copyright,  it is NOT GPL'ed text. While  the GPL is a
fantastic  idea, I  have chosen  not to  make this  freely copied  and
modified. The reasons are as follows:

1. GPL text tends to be  copied...EVERYWHERE. For example, if you look
   up a subject  on wikipedia, then try to get  more information, or a
   different perspective on  say about.com.  There you  find the EXACT
   SAME  TEXT.  This  is what  mirrors  are for.   It's an  unintended
   consequence,  but  it  can  lead  to  misinformation  being  spread
   everywhere. A bigger problem.

2. There seems to be fewer  and fewer informative websites. It used to
   be that  if you  searched for  something you  would find  a website
   about a particular  subject. Now you tend to  find the encyclopedia
   and often nothing else (well quickly).

In addition the majority of this text is quotes.

The wiki  concept is a good  idea, but they have  problems. Because no
one "owns" the  work they seem to  go to two extremes.   Either no one
maintains them, or there are edit wars. Also anyone can edit them.

**Definition of a chip set:...
**'chip set', 'chip-set' or 'chipset'?...
**What's not included:...
**Who made the first chip set?...
**Spelling errors/mistyped words...
**Info needed on:...
**A note on VESA support of 486 chipsets....
**Datasheets:...
*_IBM...
*ACC Micro...
*ALD...
*ALi...
*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
*Contaq  . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82395SX     Smart Cache                                     12/17/90
***Notes:...
**82396SX     Smart Cache                                     12/17/90
***Notes:...
***Info:...
***Versions:...
***Features:...
**82485       Turbo Cache (and 485Turbocache)                      c90...
**82489DX       Advanced Programmable Interrupt Controller    10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set                           <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
**82C822         PCIB (VLB-to-PCI bridge)                         c:94
***Notes:...
***Info:
OPTi's  82C822 VESA  local bus  to PCI  Bridge (PCIB)  chip is  a high
integration  208-pin PQFP  device designed  to work  with VESA  VL bus
compatible core logic chipsets.  The 82C822 PCIB provides interface to
the high performance PCI bus and is fully compliant to the PCI Version
2.0 specification. The 82C822 requires  no glue logic to implement the
PCI  bus interface  and hence  it allows  designers to  have  a highly
integrated  motherboard with  both VESA  local bus  and PCI  local bus
support. The PCIB chip  offers premium performance and flexibility for
VESA VL-based desktop systems running up to 50MHz. The 82C822 PCIB can
be used with  OPTi's 82C802G core logic and  82C602 buffer chipsets to
build a  low cost and  power efficient 486-based desktop  solution. It
also works  with OPTi 82C546/547  chipset to build a  high performance
PCI/VL solution based on the Intel P54C processor.

The 82C822 PCIB provides all of the control, address and data paths to
access  the PCI  bus from  the  VESA Local  bus (VL  bus). The  82C822
provides  a  complete  solution  including data  buffering,  latching,
steering, arbitration, DMA and  master functions between the 32-bit VL
bus and the 32-bit PCI bus.

The PCIB works seamlessly with  the motherboard chipset bus arbiter to
handle all requests of the host  CPU and PCI bus masters, DMA masters,
I/O relocation  and refresh. Extensive register and  timer support are
designed into the 82C822 to implement the PCI specification.

The 82C822 is a  true VESA to PCI bridge. It  has the highest priority
on  CPU accesses  after cache  and system  memory. It  generates LDEV#
automatically  and  then  compares  the addresses  with  its  internal
registers to determine whether the current  cycle is a PCI cycle. When
a cycle  is identified  as PCI  cycle, the 82C822  will take  over the
cycle and then return RDY# to the CPU. If not, the 82C822 will give up
the  cycle to  the local  device  or, in  the  case of  an ISA  slave,
generate a  BOFF# cycle to the  CPU. This action will  abort the cycle
and allow the CPU to rerun the cycle.

The 82C822 includes  registers to determine shadow  memory space, hole
locations  and sizes  to allow  the 82C822  to determine  which memory
space should be local and which is located on the ISA bus. Upon access
to memory, the 82C822 can determine whether  or not the cycle is a PCI
access by comparing the cycle with its internal registers.

***Versions:...
***Features:...
**Other:...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...