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**A note on VESA support of 486 chipsets.
Many chipsets state  that they support VESA local  bus.  In some cases
these actually  implement VLB somewhat  like PCI, where it  is entirly
decoupled from the CPU bus. Chipsets  that do not state they work with
VLB,  may  be found  on  motherboards  that  contain VLB  slots.   VLB
is  *basically*  The 486  CPU  pinout in  a  slot  form. Unless  these
m/boards contain  some additional  chips, there VLB  implementation is
directly coupled to the CPU.

**Datasheets:...
*_IBM...
*ACC Micro...
*ALD...
**Chips with no datasheet:
ALD93C305    ISA 386sx  c92
ALD93C308/A  386SX/486SLC ISA bus Single Chip 
ALD93C413    486 VLB/ISA bus Single Chip
ALD93C439    486 ?

ALD93C33     UDMA33 controller
ALD93C428    I/O controller

**93C488         5x86/486 Single Chip PCI controller            <Aug96
***Info:...
***Configurations:...
***Features:
o   Support processor bus up to 50MHz.
    - AMD 5x86-133, 486DX4-120/100, 486DX2-80/66, 486DX-50/40/33/25
    - Cyrix/IBM/ST 5x86-120/100, 486DX4-120/100, 486DX2-80/66/50, 
      486DX-40/33/25
    - TI 486DX4-100, 486DX2-80/66
    - Intel 486DX4-100/75, 486DX2-66, 486DX-40/33/25, 486SX
o   Integrated DRAM controller
    - 1Mbyte to 256Mbyte main memory
    - Non-page mode, Fast page mode, Nibble mode, Write per bit mode, 
      EDO mode DRAM providing flexible timing control
    - Supports for auto detection of memory type including size, 
      refresh cycle.
    - 4 RAS lines for 4 DRAM banks
    - Supports for symmetrical and asymmetrical DRAM addressing
    - Supports RAS only, CBR hidden refresh
    - Supports shadow memory and 384K relocated memory
o   Integrated synchronous cache controller
    - 128Kbyte to 1Mbyte cache
    - Support pipeline/non-pipeline burst SSRAM
    - Support X,1,1,1/X,2,2,2 burst cycle
o   Fast IDE interface
    - Supports up to PIO mode 4 Timings
    - Separate master/slave IDE mode support
    - Supports primary/secondary port address swapping
o   PCI bus controller
    - 4 level host to PCI write buffer
    - Supports host to PCI byte merging
    - Supports two PCI bus master
o   Integrated IPC includes
    - Two 8259 interrupt controllers
    - Two 8237 DMA controllers
    - One 8254 timer/counter
    - RTC
    - Keyboard controller
o   Power management
    - Programmable hardware events
    - Programmable CPU clock control (STPCLK#)
    - Slow down system clock speed (SLOWDWN#)
o   Single chip 208 pin QFP

*ALi...
*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
*Contaq  . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82495DX/490DX DX CPU-Cache Chip Set                           <Sep91
***Notes:...
***Info:...
***Configurations:...
***Features:...
**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...