[Home] [This version is outdated, a new version is here]
*Title...
*Search:...
*Read Me/FAQ/General Info...
**Spelling errors/mistyped words
Yes, I know there are spelling errors, and things are mistyped. It
seems no matter how hard I try my fingers hit 't' twice when typing
'compatible' rendering it 'compattible' numerous, (thousands actually)
times. I don't have the time or the will to check the spelling of
everything. Basic spell checking has been peformed. Please let me know
if there is anything that would lead to incorrect information, or
something is so mangled that it needs revising. But if you can
basically understand what was intended, just cope with it. Just
cope:-)
BTW, "110" port is an "I/O" port that has been OCRed badly, as is an
"1/0" port.
**Info needed on:...
**A note on VESA support of 486 chipsets....
**Datasheets:...
*_IBM...
*ACC Micro...
*ALD...
*ALi...
*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
*Contaq . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82379AB System I/O-APIC (SIO.A) <Dec94
***Notes:...
***Info:...
***Versions:...
***Features:
o Provides the Bridge between the PCI Bus and ISA Bus
o 100% PCI and ISA Compatible
- PCI and ISA Master/Slave Interface
- Directly Drives 10 PCI Loads and 6 ISA Slots
- Supports PCI at 25 MHz and 33 MHz
- Supports ISA from 6 MHz to 8.33 MHz
o Enhanced DMA Functions
- Compatible DMA Transfers
- 27-Bit Addressability
- Seven Independently Programmable Channels
- Functionality of Two 82C37A DMA Controllers
o Integrated Data Buffers to Improve Performance
- 8-Byte DMA/ISA Master Line Buffer
- 32-Bit Posted Memory Write Buffer to ISA
o Integrated 16-Bit BIOS Timer
o Non-Maskable Interrupts (NMI)
- PCI System Errors
- ISA Parity Errors
o Four Dedicated PCI Interrupts
- Level Sensitive
- Can be Mapped to Any Unused Interrupt
o Arbitration for ISA Devices
- ISA Masters
- DMA and Refresh
o Arbitration for PCI Devices
- Six PCI Masters Are Supported
- Fixed, Rotating, or a Combination of the Two
o Utility Bus (X-Bus) Peripheral Support
- Provides Chip Select Decode
- Controls Lower X-Bus Data Byte Transceiver
o Integrates the Functionality of One 82C54 Timer
- System Timer
- Refresh Request
- Speaker Tone Output
o Integrates the Functionality of Two 82C59 Interrupt Controllers
- 14 Interrupts Supported
- Edge/Level Selectable Interrupts; Each Interrupt Individually
Programmable
o Complete Support for SL Enhanced Intel486 CPU's
- SMI# Generation Based on System Hardware Events
- STPCLK# Generation to Power Down the CPU
o Integrated I/O Advanced Programmable Interrupt Controller (APIC)
**82380 32-bit DMA Controller w/ Integrated Peripherals 02/01/87...
**82380FB/AB PCIset: 82380FB Mobile PCI-to-PCI Bridge(MPCI2) 02/17/97...
**82384 Clock Generator and Reset Interface c86...
**82385 32-bit Cache Controller for 80386 09/29/87...
**82385SX 32-bit Cache Controller for 80386SX 01/25/89...
**82395DX High Performance Smart Cache 06/18/90...
**82395SX Smart Cache 12/17/90...
**82396SX Smart Cache 12/17/90...
**82485 Turbo Cache (and 485Turbocache) c90...
**82489DX Advanced Programmable Interrupt Controller 10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94
***Notes:...
***Info:...
***Configurations:...
***Features:...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...
(c) Copyright mR_Slugs Warehouse - All rights Reserved