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**82379AB     System I/O-APIC (SIO.A)                           <Dec94
***Notes:...
***Info:...
***Versions:...
***Features:...
**82380       32-bit DMA Controller w/ Integrated Peripherals 02/01/87...
**82380FB/AB  PCIset: 82380FB Mobile PCI-to-PCI Bridge(MPCI2) 02/17/97...
**82384       Clock Generator and Reset Interface                  c86...
**82385       32-bit Cache Controller for 80386               09/29/87...
**82385SX     32-bit Cache Controller for 80386SX             01/25/89...
**82395DX     High Performance Smart Cache                    06/18/90...
**82395SX     Smart Cache                                     12/17/90...
**82396SX     Smart Cache                                     12/17/90...
**82485       Turbo Cache (and 485Turbocache)                      c90...
**82489DX       Advanced Programmable Interrupt Controller    10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set                           <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99
Chips:         
Memory Access Controller (MAC)  
Data Interface Buffer (DIB)
CPUs:          8x P-III Xeon Oct
DRAM Types:    SDRAM PC100 2-way Interleave dual channel
Max Mem:       32GB
ECC/Parity:    ECC
AGP speed:     N/A
Bus Speed:     100
PCI Clock/Bus: 1/3 PCI-66/64



**800 series...
*Headland/G2...
**HT21          386SX/286 Single Chip (20 MHz)                 c:Aug91
***Info:...
***Configurations:...
***Features:
o   Single Chip 80386SX/286 PC/AT Compatible Solution for CPU Clock 
    Speeds to 20MHz
o   SX Mode or 286 Mode
o   Supports up to 8 MB DRAM using 1M or 256K Devices in by 1 or 4 
    configuration
o   Page Mode and 2 or 4-Way Interleaving
o   LIM EMS 4.0 Support in Hardware using 2 Sets of 32 EMS Registers
o   8-Bit or 16-Bit BIOS Support
o   Asynchronous AT Bus Clock
o   Supports up to 12 MHz Backplane Operation
o   Programmable DRAM Timing
o   Port 92 Alternate GATEA20 and Hot Reset
o   Shadow RAM support over entire C0000-DFFFF range in 16K 
    increments
o   BIOS Shadow support in 64K increments
o   Built-in Sleep Mode
o   Three-state control pins for board level testing
o   HCMOS Technology

**HT22          386SX/286 Single Chip (25 MHz)                 c:Sep91...
**HT25          3-volt Core Logic for 386SX                    c:Dec92...
**HT35          Single-Chip Peripheral Controller [partial info]     ?...
**HTK320        386DX Chip Set                                 c:Sep91...
**HTK340        "Shasta" 486 Chip Set                          c:Jun92...
**Support Chips:
**HT44          Secondary Cache                                c:Jun92...
**Other:...
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