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**82378 System I/O (SIO) (82378IB and 82378ZB) c:Mar93
***Notes:
Information taken from: 82420_PCIset_ISA_and_EISA_Bridges_Mar93.pdf
Intel_Peripheral_Components_1994.pdf*
1995_Intel_Pentium_Processors_and_Related_Components.pdf*2
82378 (Mar-96).pdf
(Errata:1) http://support.intel.com/support/chipsets/420/8510.htm*3
(Errata:2) http://support.intel.com/support/chipsets/420/8511.htm*3
>* datasheet for 82378 is dated Oct'93
>*2 datasheet for 82378 is dated Dec'94
>*3 see archived sources at the end of this section
The March '93 source makes no mention of the ZB variant, indicating
it was released after this date. The Oct'93 datasheet is only 2
pages, a full length version could not be found. Most differences
between the Mar'93 and the Oct'93 are indicated in the text. In
addition, the Mar'93 refers to the 82378IB specifically, the Oct'93
refers to the 82378 in general, and briefly explains the differences
between the IB and ZB variants.
The main difference between the IB and ZB variants is the number of
supported PCI masters and interrupts. The mar'93 datasheet claims that
the IB variant supports four. The Oct'93 source updates this by
claiming it only supports two and states that only the ZB variant
supports four. Perhaps the Mar'93 datasheet is a misprint, or the
chip didn't meet it's intended specification.
In Errata:1, more specifics are given. Dated Aug'93 the following
diff- erences are given:
"
82378IB * Name change from 82378IB to 82378ZB
Changes: * ZB eliminates all known IB errata
* Features/Enhancements include: Interrupt Steering Logic,
System Management Mode (SMM), leadframe change from copper
to Alloy 42.
Timing:
We anticipate production shipments for the 82378ZB to begin in
December 1993..."
Errata:2 gives further details. The document itself is undated, but
Errata:1 is hyperlinked to it. Its text is quoted in the Versions
section.
The Dec'94 datasheet makes no mention of either variant, it just
refers to the 82378. It would appear that this is the ZB variant. The
biggest change is again to the PCI masters. Now it supports 6 PCI
masters and still 4 PCI interrupts. It also now supports Advanced
Power Management. Differences are shown in the text. There are some
additional insignificant minor differences in the text not shown.
The Mar'96 datasheet again refers to the 82378ZB specifically. This
indicates that the chip described in the Dec'94 is *likely* the ZB
variant. This datasheet describes the 82378ZB and the 82379AB. Changes
in this datasheet have not been added to the quoted text below.
Archived sources:
http://web.archive.org/web/20000816013859/http://support.intel.com/support/chipsets/420/8510.htm
http://web.archive.org/web/20000816013854/http://support.intel.com/support/chipsets/420/8511.htm
***Info:...
***Versions:...
***Features:...
**82379AB System I/O-APIC (SIO.A) <Dec94...
**82380 32-bit DMA Controller w/ Integrated Peripherals 02/01/87...
**82380FB/AB PCIset: 82380FB Mobile PCI-to-PCI Bridge(MPCI2) 02/17/97...
**82384 Clock Generator and Reset Interface c86...
**82385 32-bit Cache Controller for 80386 09/29/87...
**82385SX 32-bit Cache Controller for 80386SX 01/25/89...
**82395DX High Performance Smart Cache 06/18/90...
**82395SX Smart Cache 12/17/90...
**82396SX Smart Cache 12/17/90...
**82485 Turbo Cache (and 485Turbocache) c90...
**82489DX Advanced Programmable Interrupt Controller 10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99
Chips:
Memory Access Controller (MAC)
Data Interface Buffer (DIB)
CPUs: 8x P-III Xeon Oct
DRAM Types: SDRAM PC100 2-way Interleave dual channel
Max Mem: 32GB
ECC/Parity: ECC
AGP speed: N/A
Bus Speed: 100
PCI Clock/Bus: 1/3 PCI-66/64
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
**5591/5592/5595 (David) Pentium PCI A.G.P. Chipset <01/09/98
***Info:...
***Configurations:...
***Features:
o Support Intel/AMD/Cyrix Pentium CPU and Other Compatible CPU
Host Bus at 60/66 MHz and 3.3V Bus Interface
− Support the Pipelined Address of Pentium compatible CPU
− Support the Linear Address Mode of Cyrix CPU
o Support the Pipelined Address Mode of Pentium CPU
o Fully Compliant to A.G.P. Revision 1.0 Specification
o Meet PC97 Requirements
o Supports PCI Revision 2.1 Specification
o Integrated Second Level (L2) Cache Controller
- Write Back Cache Mode
- Support L2 Cache Flushing for entire L2 cache or specific
4K page
- 8 bits or 7 bits Tag with Direct Mapped Cache Organization
- Integrated 32K bits Dirty SRAM
- Integrated 32K bits Invalid SRAM
- Support Pipelined Burst SRAM
- Support 256K/512K/1MBytes Cache Sizes
- Cache Hit Read/Write Cycle of 3-1-1-1
- Cache Back-to-Back Read/Write Cycle of 3-1-1-1-1-1-1-1
- Support Single Read Allocation for L2 Cache
- Support Concurrency of CPU to L2 cache and A.G.P. master to
DRAM accesses
o Integrated DRAM Controller
- Support 6 RAS Lines for FPM/EDO/SDRAM DIMMs/SIMMs
- Support 2Mbytes to 768Mbytes of main memory
- Support Cacheable DRAM Sizes up to 256 MBytes.
- Support 256K/512K/1M/2M/4M/8M/16Mx N FPM/EDO/SDRAM DRAM
- Support 64 Mb DRAM Technology
- Support Parity Checker or ECC Function
- Support 3.3V or 5V DRAM
- Supports Symmetrical and Asymmetrical DRAM
- Support Concurrent Write Back
- Support CAS before RAS Refresh, Self Refresh
- Support Relocation of System Management Memory
- Programmable CAS#, RAS#, RAMWE# and MA Driving Current
- Fully Configurable for the Characteristic of Shadow RAM (640
KBytes to 1 MBytes)
- Support FPM DRAM 5/6-3-3-3(-3-3-3-3) Burst Read Cycles
- Support EDO DRAM 5/6-2-2-2(-2-2-2-2) Burst Read Cycles
- Support SDRAM 5/6/7-1-1-1(-2/3-1-1-1) Burst Read Cycles
- Support X-1-1-1/X-2-2-2/X-3-3-3 Burst Write Cycles
- Two Programmable Non-cacheable Regions
- Option to Disable Local Memory in Non-cacheable Regions
- Shadow RAM in Increments of 16 Kbytes
- Pseudo Directory/Page Scheme for Mapping Graphical Texture
Access to Physical Memory Address
- Built-in 8 Way Associative/16 Entries GART cache to Minimize the
Number of Memory Bus Cycles Required for Accessing Graphical
Texture Memory
- Programmable Counters to Ensure Guaranteed Minimum Access Time
for A.G.P., CPU, and PCI accesses
o Provides High Performance PCI Arbiter.
- Support up to 5 PCI Masters
- Support Rotating Priority Mechanism
- Hidden Arbitration Scheme Minimizes Arbitration Overhead.
- Support Concurrency between CPU to Memory and PCI to PCI
- Support Concurrency between CPU to 33Mhz PCI Access and 33Mhz
PCI to A.G.P. Access
- Support Concurrency between CPU to 66Mhz PCI Access and A.G.P.
to 33Mhz PCI Access
- Programmable Timers Ensure Guaranteed Minimum Access Time for
PCI Bus Masters, and CPU
o Integrated Host-to-PCI Bridge
- Support Asynchronous and Synchronous PCI Clock
- Translates the CPU Cycles into the PCI Bus Cycles
- Zero Wait State Burst Cycles
- Support IDE Posted Write
- Support Pipelined Process in CPU-to-PCI Access
- Support Advance Snooping for PCI Master Bursting
- Maximum PCI Burst Transfer from 256 Bytes to 4 Kbytes
- Support Memory Remapping Function for PCI master accessing
Graphical Window
o Integrated A.G.P. Compliant Target/66Mhz Host-to-PCI Bridge
- Support Asynchronous and Synchronous A.G.P. Clock
- Support 1X, and 2X Mode for A.G.P. 66/133 MHz 3.3V device
- Support Graphic Window Size from 4Mbytes to 256Mbytes
- Different arbitration policy for A.G.P. devices and 66Mhz PCI
devices.
- Translates Sequential CPU-to-A.G.P. Memory Write Cycles into
A.G.P. Bus (PCI66) Burst Cycles
- Zero Wait State Burst Cycles
- Support Pipelined Process in CPU-to-A.G.P. Access
- Support Advance Snooping for A.G.P. Master initiate system
memory access with PCI Cycles
- Support 8 Way, 16 Entries Page Table Cache to enhance A.G.P.
Read/Write Performance
- Support Both 1-Level and 2-Level GART (Graphic Address Re-
Mapping Table)
- Maximum PCI Burst Transfer from 256 Bytes to 4 Kbytes
- Programmable Counters to Ensure Guaranteed Minimum Access Time
for Low Priority Request, CPU to A.G.P./and A.G.P. Master
Transaction
- Support PCI-to-PCI bridge function for memory write from 33Mhz
PCI bus to A.G.P. bus
o Integrated Posted Write Buffers and Read Prefetch Buffers to
Increase System Performance
- CPU-to-Memory Posted Write Buffer (CTMFF) with 8 QW Deep, Always
Sustains 0 Wait Performance on CPU-to-Memory
- CPU-to-Memory Read Buffer with 4 QW Deep
- CPU-to-PCI Posted Write Buffer(CTPFF) with 8 DW Deep
- PCI-to-Memory Posted Write Buffer(PTHFF) with 8 QW Deep, Always
Streams 0 Wait Performance on PCI-to/from-Memory Access
- PCI-to-Memory Read Prefetch Buffer(CTPFF) with 8 QW Deep
- CPU-to-PCI66 Posted Write Buffer(CTAFF) with 8 DW Deep
- PCI66-to-Memory Posted Write Buffer(ATHFF) with 8 QW Deep
- A.G.P. Request Queue With the Depth of 32
- A.G.P. High Priority Write Queue with 64 QW Deep
- A.G.P. Low Priority Write Queue with 64 QW Deep
- A.G.P. High Priority Read Return Queue with 64 QW Deep
- A.G.P. Low Priority Read Return Queue with 64 QW Deep
o Fast PCI IDE Master/Slave Controller
- Bus Master Programming Interface for ATA Windows 95 Compliant
Controller
- Plug and Play Compatible
- Support Scatter and Gather
- Support Dual Mode Operation - Native Mode and Compatibility
Mode
- Support IDE PIO Timing Mode 0, 1, 2 ,3 and 4
- Support Multiword DMA Mode 0, 1, 2
- Support Ultra DMA/33
- Two Separate IDE Bus
- Two 16 DW FIFO for PCI Burst Transfers.
o Support NAND Tree for Ball Connectivity Testing
o 553-Balls BGA Package
o 0.35μm 3.3V CMOS Technology
**5596/5513 (Genesis) Pentium PCI Chipset <03/26/96...
**5597/5598 (Jedi) Pentium PCI/ISA Chipset <04/15/97...
**530/5595 (Sinbad) Host, PCI, 3D Graphics & Mem. Ctrl.<11/10/98...
**540 (Spartan) Super7 2D/3D Ultra-AGP Single C.S.<11/30/99...
**55x SoC (System-on-chip) <03/14/02...
**
**Support chips:
**85C206 Integrated Peripheral Controller [no datasheet] ?...
**5595 Pentium PCI System I/O <12/24/97...
**950 LPC I/O <07/16/99...
**Other:...
**PII/III/Pro...
**Athlon etc...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...
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