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**A note on VESA support of 486 chipsets.
Many chipsets state  that they support VESA local  bus.  In some cases
these actually  implement VLB somewhat  like PCI, where it  is entirly
decoupled from the CPU bus. Chipsets  that do not state they work with
VLB,  may  be found  on  motherboards  that  contain VLB  slots.   VLB
is  *basically*  The 486  CPU  pinout in  a  slot  form. Unless  these
m/boards contain  some additional  chips, there VLB  implementation is
directly coupled to the CPU.

**Datasheets:...
*_IBM...
*ACC Micro...
**ACC2020    Power Management Chip                                 c92
***info:...
***Versions:...
***Features:
o   Provides eight trigger input channels for monitoring activities 
    such as keyboard, video, hard disk, floppy disk, and user defined 
    device.
o   Provides eight power control outputs
o   Each power control output status can be determined by the 
    combinations of the eight trigger inputs
o   Provides eight user programmable time-out timers.
o   Flexible timer scales:
      2 timers from 1/8 second to 14 seconds
      4 timers from 1 minute to 15 minutes
      1 timer from 2 minutes to 210 minutes
      1 timer from 4 minutes to 7 hours
o   Each trigger input can select one of the two timer scales
o   No glitch CPU clock switching functions
o   Supports CPU clock up to 66 MHz
o   Generates 16 MHz clock for AT Bus
o   Generates 32.768 KHz for both RTC and Ao02020 by using 32.768 KHz 
    crystal
o   Supports Modem ring power-on
o   Supports scheduled power-on
o   Supports cover switch power-down/on
o   Supports Suspend and Resume
o   Provides six operation modes:
      Full Operation mode
      Rest mode
      Standby mode
      Shutdown mode
      Freeze mode
      Off mode
o   Predefined mode transition among Normal Rest. and Standby modes
o   Programmable transitions of operation modes
o   Provides interrupt request for suspend resume operation
o   Interrupt request output can be masked
o   Supports Programmable Slow Refresh in Shutdown and Freeze modes
o   Supports CAS before RAS refresh
o   80-pin QFP

**ACC5500    Multifunction I/O Control Chip for PS2 Model 50/60    c88...
**
**Other chips...
*ALD...
*ALi...
*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
*Contaq  . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82495DX/490DX DX CPU-Cache Chip Set                           <Sep91
***Notes:...
***Info:...
***Configurations:...
***Features:...
**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...