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**Spelling errors/mistyped words
Yes, I  know there are  spelling errors,  and things are  mistyped. It
seems no matter  how hard I try  my fingers hit 't'  twice when typing
'compatible' rendering it 'compattible' numerous, (thousands actually)
times.  I  don't have the  time or the will  to check the  spelling of
everything. Basic spell checking has been peformed. Please let me know
if  there is  anything that  would lead  to incorrect  information, or
something  is so  mangled  that  it needs  revising.  But  if you  can
basically  understand  what was  intended,  just  cope with  it.  Just
cope:-)

BTW, "110" port is  an "I/O" port that has been OCRed  badly, as is an
"1/0" port.

**Info needed on:...
**A note on VESA support of 486 chipsets....
**Datasheets:...
*_IBM...
*ACC Micro...
*ALD...
*ALi...
*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
*Contaq  . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82430TX     PCIset (Pentium) TX (Triton II) (82439TX)       02/17/97
***Notes:...
***Info:...
***Configurations:...
***Features:
o   Supports Mobile and Desktop
o   Supports the Pentium Processor Family Host Bus at 66 MHz and 
    60 MHz at 3.3V and 2.5V
o   PCI 2.1 Compliant
o   Integrated Data Path
o   Integrated DRAM Controller
    - 4 Mbytes to 256 MBytes main memory
    - 64-Mbit DRAM/SDRAM Technology Support
    - FPM (Fast Page Mode), ED0 and SDRAM DRAM Support
    - 6 RAS Lines Available
    - Integrated Programmable Strength for DRAM Interface
    - CAS-Before-RAS Refresh, Extended Refresh and Self 
      Refresh for EDO
    - CAS-Before-RAS and Self Refresh for SDRAM
o   Integrated L2 Cache Controller
    - 64MB DRAM Cacheability
    - Direct Mapped Organization-Write Back Only
    - Supports 256K and 512K Pipelined Burst SRAM and DRAM Cache
      SRAM
    - Cache Hit Read/Write Cycle Timings at 3-1-1-1
    - Back-to-Back Read/Write Cycles at 3-1-1-1-1-1-1-1
    - 64K x 32 SRAM also supported
o   Fully Synchronous, Minimum Latency 30/33-MHz PCI Bus Interface
    - Five PCI Bus Masters (including PIIX4)
    - 10 DWord PCI-to-DRAM Read Prefetch Buffer
    - 18 DWord PCI-DRAM Post Buffer
    - Multi-Transaction Timer to Support Multiple Short PCI 
      Transactions
o   Power Management Features
    - PCI CLKRUN# Support
    - Dynamic Stop Clock Support
    - Suspend to RAM (STF)
    - Suspend to Disk (STD)
    - Power On Suspend (POS)
    - internal Clock Control
    - SDRAM and EDO Self Refresh During Suspend
    - ACPI Support
    - Compatible SMRAM (C_SMRAM) and Extended SMRAM (E_SMRAM)
    - SMM Writeback Cacheable in E_SMRAM Mode up to 1 MB
    - 3.3/5V DRAM, 3.3/5V PCI 3.3/5V Tag and 3.3/2.5 SRAM Support
o   Test Features
    - NAND Tree Support for all Pins
o   Supports the Universal Serial Bus (USB)
o   324-Pin MBGA 430TX PCIset Xcelerated Controller (MTXC) with
    integrated Data Paths


**82450KX/GX  PCIset (Pentium Pro) KX/GX (Mars/Orion)         11/01/95...
**
**Support Chips:
**82091AA     Advanced Interface Peripheral (AIP)                  c93...
**8289        Bus Arbiter (808x)                                   c79...
**82289       Bus Arbiter for iAPX 286 Processor Family            c83...
**82258       Advanced Direct Memory Access Coprocessor(ADMA) 01/01/84...
**82335       High-Integration Interface Device For 386SX      c:Nov88...
**82360SL     I/O Subsystem                                   10/05/90...
**82370       Integrated System Peripheral (for 82376)         c:Oct88...
**82371FB/SB  PCI ISA IDE Xcelerator 82371FB/82371SB (PIIX/3) 01/31/95...
**82371MX     Mobile PCI I/O IDE Xcelerator (MPIIX)           11/01/95...
**82371AB     PCI-TO-ISA / IDE Xcelerator 82371AB (PIIX4)     02/17/97...
**82374/82375 PCI-EISA Bridge (82374EB/82375EB, 374SB/375SB)   c:Mar93...
**82378       System I/O (SIO) (82378IB and 82378ZB)           c:Mar93...
**82379AB     System I/O-APIC (SIO.A)                           <Dec94...
**82380       32-bit DMA Controller w/ Integrated Peripherals 02/01/87...
**82380FB/AB  PCIset: 82380FB Mobile PCI-to-PCI Bridge(MPCI2) 02/17/97...
**82384       Clock Generator and Reset Interface                  c86...
**82385       32-bit Cache Controller for 80386               09/29/87...
**82385SX     32-bit Cache Controller for 80386SX             01/25/89...
**82395DX     High Performance Smart Cache                    06/18/90...
**82395SX     Smart Cache                                     12/17/90...
**82396SX     Smart Cache                                     12/17/90...
**82485       Turbo Cache (and 485Turbocache)                      c90...
**82489DX       Advanced Programmable Interrupt Controller    10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set                           <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94
***Notes:...
***Info:...
***Configurations:...
***Features:...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...