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**82350DT EISA Chip Set 04/22/91
***Notes:...
***Info:
****General:...
****82351 Local I/O EISA Support Peripheral (LIO.E)...
****82352DT EISA Bus Buffer (EBB)...
****82353 Advanced Data Path Device...
****82357 Integrated System Peripheral (ISP)...
****82358DT EISA Bus Controller...
****82359 DRAM Controller...
****82355 Bus Master Interface Controller (BMIC)
The 82355 Bus Master Interface Controller (BMIC) is a highly
integrated Bus Master designed for use in 32-Bit EISA Bus Master
expansion board designs and supports all of the enhancements defined
in the EISA specifications required for EISA bus master applications.
The BMIC provides a simple, yet, powerful and flexible interface
between the functions on the expansion board and the EISA bus. With
the help of external buffer devices, the BMIC provides all EISA
control, address, and data signals necessary to interface to the EISA
bus.
The primary function of the 82355 is to support 16- and 32-bit burst
data transfers between functions on the EISA expansion board and the
EISA bus. Data transfer rates of up to 33 Mbytes/sec are supported
(the fastest transfer rate available on an EISA bus). The following
logic on the BMIC supports efficient burst transfers:
o Arbitration logic, for gaining control of the EISA bus
o Two transfer-address and byte counters
o Two data FIFOs, which allow expansion board and EISA bus timing to
operate asynchronously
o Data shifters, which align data to specific byte boundaries
o A transfer buffer interface, for the data transfers on the expansion
board
o General-purpose command and status interface logic
o Local processor interface, to allow programming by an on-board
processor
o EISA slave interface, to allow communication with the EISA system
The BMIC greatly simplifies the design of EISA expansion boards, With
the 82355, a board can be implemented with simple logic similar to
that used in traditional ISA DMA designs. The EISA standard allows
designs with 32-bit data and address buses, burst transfers, and
automatic handling of the full EISA bus master protocol.
To maximize system throughput, the 82355 BMIC incorporates three fully
concurrent interfaces: EISA interface, Transfer Buffer Interface, and
Local Processor interface. The EISA interface incorporates two
24-byte FIFOs, and implements the full EISA protocol. The Transfer
Buffer interface is optimized for high speed static RAM buffers, and
can operate at a maximum frequency of 20 MHz. The Local Processor
interface supports a generic slave interface, and allows the local
processor to fully program the BMIC for operation. Local processors
are supported with the ability to access individual locations in
system memory or I/O space; this peek-and-poke feature allows the
expansion board to communicate easily with other devices in the
system. All three interfaces can operate simultaneously, thus
maximizing overall system performance.
Address-generation support for the data transfer buffer logic on the
expansion board is provided onchip. The transfer logic on the
expansion board can use a high-speed asynchronous transfer clock. The
BMIC handles all synchronization with the EISA bus. A FIFO within the
BMIC eliminates performance degradation on burst transfers caused by
synchronization delays. The BMIC also provides a set of program-
mable address comparators that drive external chip selects on the
expansion board to assist local devices in decoding I/O address
ranges.
***Configurations:...
***Features:...
**82420TX/ZX PCIset (for 486) TX (Saturn), ZX (Saturn II) c:Nov92...
**82420EX PCIset (for 486) EX (Aries) (82425EX/82426EX) <Dec94...
**82430LX PCIset (Pentium) LX (Mercury) (82433LX/82434LX) 03/22/93...
**82430NX PCIset (Pentium) NX (Neptune) (82433NX/82434NX) Mar94...
**82430FX PCIset (Pentium) FX (Triton I) (82437FX/82438FX)01/31/95...
**82430MX PCIset (Pentium) MX (Mobile Triton)(82437/438MX)11/01/95...
**82430HX PCIset (Pentium) HX (Triton II) (82439HX) 02/12/96...
**82430VX PCIset (Pentium) VX (Triton II) (82437VX/82438) 02/12/96...
**82430TX PCIset (Pentium) TX (Triton II) (82439TX) 02/17/97...
**82450KX/GX PCIset (Pentium Pro) KX/GX (Mars/Orion) 11/01/95...
**
**Support Chips:
**82091AA Advanced Interface Peripheral (AIP) c93...
**8289 Bus Arbiter (808x) c79...
**82289 Bus Arbiter for iAPX 286 Processor Family c83...
**82258 Advanced Direct Memory Access Coprocessor(ADMA) 01/01/84...
**82335 High-Integration Interface Device For 386SX c:Nov88...
**82360SL I/O Subsystem 10/05/90...
**82370 Integrated System Peripheral (for 82376) c:Oct88...
**82371FB/SB PCI ISA IDE Xcelerator 82371FB/82371SB (PIIX/3) 01/31/95...
**82371MX Mobile PCI I/O IDE Xcelerator (MPIIX) 11/01/95...
**82371AB PCI-TO-ISA / IDE Xcelerator 82371AB (PIIX4) 02/17/97...
**82374/82375 PCI-EISA Bridge (82374EB/82375EB, 374SB/375SB) c:Mar93...
**82378 System I/O (SIO) (82378IB and 82378ZB) c:Mar93...
**82379AB System I/O-APIC (SIO.A) <Dec94...
**82380 32-bit DMA Controller w/ Integrated Peripherals 02/01/87...
**82380FB/AB PCIset: 82380FB Mobile PCI-to-PCI Bridge(MPCI2) 02/17/97...
**82384 Clock Generator and Reset Interface c86...
**82385 32-bit Cache Controller for 80386 09/29/87...
**82385SX 32-bit Cache Controller for 80386SX 01/25/89...
**82395DX High Performance Smart Cache 06/18/90...
**82395SX Smart Cache 12/17/90
***Notes:...
**82396SX Smart Cache 12/17/90...
**82485 Turbo Cache (and 485Turbocache) c90...
**82489DX Advanced Programmable Interrupt Controller 10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
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