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**82350DT EISA Chip Set 04/22/91
***Notes:...
***Info:
****General:...
****82351 Local I/O EISA Support Peripheral (LIO.E)...
****82352DT EISA Bus Buffer (EBB)...
****82353 Advanced Data Path Device...
****82357 Integrated System Peripheral (ISP)...
****82358DT EISA Bus Controller
The 82358DT EISA Bus Controller is part of Intel's 82350 and 82350DT
chip sets. There are five mode or function select pins which allow the
82358DT to be programmed for use in either 82350 or 82350DT based
systems. The mode pins also provide support for posted memory write
cycles to the EISA/ISA bus and Intel486 burst support. The 82358DT
defaults to 82350 mode and is 100% socket compatible with the 82358
(EBC).
The 82358DT interfaces the 386 and Intel486 microprocessors to the
Extended Industry Standard Architecture (EISA) bus. It is used to
facilitate bus cycles between the Host (CPU) bus and the EISA/ISA
bus. In an 82350 system, the 82358DT interfaces to the cycle address
and control signals of the Host bus. In an 82350DT system, the 82358DT
interfaces to the cycle address and control signals of the 82359 DRAM
controller. The 82358DT generates the appropriate data conversion and
alignment control signals to implement an external byte assembly/
disassembly mechanism for transferring data of different widths
between the Host, EISA, and Industry Standard Architecture (ISA)
buses. It also provides the cycle translation between the Host, EISA,
and ISA buses.
The 82358DT is tightly coupled with the 82357 DMA controller (ISP) to
run 8-. 16-, or 32-Sit EISA/ISA DMA transfers.
The 82358DT features hardware enforced I/O recovery logic to provide
I/O recovery time between back-to-back I/O cycles.
The 82358DT provides special cache hardware interface signals to
implement a high performance 386 based system with an 82385 or 82395
cache, controller.
The 82358DT also provides resets to the Inte1486, 80386, 82385, and
other devices in the system to provide an integrated synchronous
system reset.
2.0 INTRODUCTION
All descriptions in this document apply to both the 386 and i486
CPU. and the 82350 and 82350DT systems, unless otherwise stated.
2.1 82358DT System Architecture Overview
The 82358DT EISA Bus Controller is mode selectable to operate in
either an 82350 or an 82350DT system environment, (refer to Figures
2-1 through 2-3)[see datasheet]. In an 82350DT environment, the
82358DT is further mode selectable to operate in either an enhanced or
buffered configuration. A detailed discussion on the various 82358DT
modes and configurations can be found in section 4.1
The 82358DT is located between the host (CPU) bus and the EISA/ISA
bus, and provides the control signal translations necessary for bus to
bus transfers. Cycles initiated on either bus are tracked by the
82358DT. The 82358DT translates EISA to ISA, ISA to EISA, and Host to
EISA or ISA cycles. The 82358DT also breaks down bus cycles so that
transfers between buses of different sizes or misaligned addresses
function correctly. The data byte swap logic and address buffer
control signals are generated directly from the 82358DT. These signals
are used, to control the 82353 Advanced Data Path (ADP) and the EISA
Bus Buffer (EBB) devices.
In an 82350 based system, the 82358DT tracks and interfaces directly
to the host bus In an 82350DT based system, the 82358DT tracks host
initiated cycles through the 82359 DRAM controller. When a host bus
master initiates a cycle, and no host slave responds, the 82358DT
forwards the cycle to the EISA/ISA bus. If back-to-back ISA I/O cycles
are torwarded to the ISA bus, the 82358DT will insert delays between
the back-to-back cycles for the purpose of I/O recovery. If a memory
write cycle is forwarded to either an EISA or ISA slave, the 82358DT
has the support capability to post the cycle.
The 82358DT provides the bridge between ISA and EISA devices on the
EISA/ISA bus. The 82358DT translates cycles from EISA masters into
cycles that ISA slaves can understand. Similarly, it translates cycles
initiated by ISA masters into cycles that EISA slaves can understand.
The 82358DT also performs byte assembly/disassembly for data transfers
between devices on the EISA/ISA bus of varying data Widths.
The 82357 Integrated System Peripheral (ISP) which contains the high
performance EISA-compatible DMA controller. EISA arbitration,
interrupt controller, refresh Logic, and other integrated peripheral
functions, interfaces to the 82358DT When requested by the ISP, the
82358DT runs EISA or ISA bus cycles for DMA transfers and memory
refreshes.
The 82350 system architecture is based on Intel’s 82350 chipset. This
chip set includes the 82358DT EISA bus controller, 82357 Integrated
System Peripheral (ISP). and the 82352 EISA bus buffers (EBB).
The 82358DT provides the data and cycle translation between the host,
EISA, and ISA buses during host, EISA, ISA, and DMA master cycles. The
ISP provides the DMA function, refresh, system arbitration, interrupt
control, timer/counter functions, and NMI control. The EBB provides
the data swap logic and address path between the host, EISA, and ISA
buses, and the data parity during memory accesses.
Also part of the EISA solution is the 82355 Bus Master Interface
controller (BMIC). The BMIC provides the EISA bus master functions
necessary to interface a bus master add-in board to the EISA bus.
The 82350 system architecture supports the 33 and 25 MHz 386 and i486
microprocessors.
The 82350DT/enhanced system architecture is a superset of Intel's
82350 chip set. The 82350DT chip set builds upon the 82350 chip set by
adding the following Integrated functions: dual ported memory
control, serial port support bi-directional parallel port support,
and real time clock support. To provide this additional support, the
82359 DRAM controller, 82353 Advanced Data Path (ADP) and the 82351
local I/O (LIOE) have been added to provide the 82350DT chip set
functions.
EISA operation is unchanged in the 82350DT/buffered configuration.
This configuration differs from the 82350DT/enhanced configuration in
that a high speed bus (buffered bus) similar to the host bus has been
added between the 82358DT and 82359. The buttered bus can be used by
peripheral device to access main memory at higher speeds than allowed
on the EISA or ISA buses. This bus is transparent to the
82358DT. Peripheral devices located on this bus are treated as host
devices.
****82359 DRAM Controller...
****82355 Bus Master Interface Controller (BMIC)...
***Configurations:...
***Features:...
**82420TX/ZX PCIset (for 486) TX (Saturn), ZX (Saturn II) c:Nov92...
**82420EX PCIset (for 486) EX (Aries) (82425EX/82426EX) <Dec94...
**82430LX PCIset (Pentium) LX (Mercury) (82433LX/82434LX) 03/22/93...
**82430NX PCIset (Pentium) NX (Neptune) (82433NX/82434NX) Mar94...
**82430FX PCIset (Pentium) FX (Triton I) (82437FX/82438FX)01/31/95...
**82430MX PCIset (Pentium) MX (Mobile Triton)(82437/438MX)11/01/95...
**82430HX PCIset (Pentium) HX (Triton II) (82439HX) 02/12/96...
**82430VX PCIset (Pentium) VX (Triton II) (82437VX/82438) 02/12/96...
**82430TX PCIset (Pentium) TX (Triton II) (82439TX) 02/17/97...
**82450KX/GX PCIset (Pentium Pro) KX/GX (Mars/Orion) 11/01/95...
**
**Support Chips:
**82091AA Advanced Interface Peripheral (AIP) c93...
**8289 Bus Arbiter (808x) c79...
**82289 Bus Arbiter for iAPX 286 Processor Family c83...
**82258 Advanced Direct Memory Access Coprocessor(ADMA) 01/01/84...
**82335 High-Integration Interface Device For 386SX c:Nov88...
**82360SL I/O Subsystem 10/05/90...
**82370 Integrated System Peripheral (for 82376) c:Oct88...
**82371FB/SB PCI ISA IDE Xcelerator 82371FB/82371SB (PIIX/3) 01/31/95...
**82371MX Mobile PCI I/O IDE Xcelerator (MPIIX) 11/01/95...
**82371AB PCI-TO-ISA / IDE Xcelerator 82371AB (PIIX4) 02/17/97...
**82374/82375 PCI-EISA Bridge (82374EB/82375EB, 374SB/375SB) c:Mar93...
**82378 System I/O (SIO) (82378IB and 82378ZB) c:Mar93...
**82379AB System I/O-APIC (SIO.A) <Dec94...
**82380 32-bit DMA Controller w/ Integrated Peripherals 02/01/87...
**82380FB/AB PCIset: 82380FB Mobile PCI-to-PCI Bridge(MPCI2) 02/17/97...
**82384 Clock Generator and Reset Interface c86...
**82385 32-bit Cache Controller for 80386 09/29/87...
**82385SX 32-bit Cache Controller for 80386SX 01/25/89...
**82395DX High Performance Smart Cache 06/18/90...
**82395SX Smart Cache 12/17/90
***Notes:...
**82396SX Smart Cache 12/17/90...
**82485 Turbo Cache (and 485Turbocache) c90...
**82489DX Advanced Programmable Interrupt Controller 10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
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