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**82350DT EISA Chip Set 04/22/91
***Notes:...
***Info:
****General:...
****82351 Local I/O EISA Support Peripheral (LIO.E)...
****82352DT EISA Bus Buffer (EBB)...
****82353 Advanced Data Path Device
The 82353 is a highly integrated data path device. It is used in
conjunction with the 82359 DRAM controller to implement a high
performance dual ported memory controller. Each 82353 is 16-bit
slice. Multiple 82353s can be used for those systems which have 32 or
64 bit data busses. The memory interface of the 82353 is very
flexible in that it can interface to either 16-, 32-, or 64-bit memory
array to a 16-bit Host and System Bus. When using two 82353s in
parallel, the resultant 128-bit memory bus allows for i486 bursts to
complete in 0 wait state. Other features include an integrated posted
write latch, internal parity generation/checking logic, and integrated
byte assembly/disassembly logic.
2.0 INTRODUCTION
The 82353 Advanced Data Path (ADP), works closely with the 82359 EISA
DRAM Controller to provide an extremely flexible system conforming to
the EISA bus specification.
The 82353 ADP and associated 82359 DRAM Controller provide a unique
bus structure, utilizing two distinct electrically isolated buses one
bus, labeled "Host Bus", accommodates the host CPU/cache combination.
The second bus, labeled "System Bus" accommodates standard I/O and
add-in peripherals and follows EISA timings. Each of the busses have
their own address/data path to main memory.
The 82353 provides a dual ported data path between the system and host
data bus to the DRAM data bus. This dual ported architecture allows
accesses to DRAM by host masters without incurring arbitration.
Integrated into the 82353 are first and second level posted write
latches to support zero wait state writes. A burst read or write
capability of up to 16 sequential words is provided.
A single 82353 is a 16-bit data path slice which interfaces to 16-bit
host and system data buses. The intent of the 82353 is for two 82353’s
to be connected in parallel, providing a 32-bit host and system data
bus and 32. 64. or 128-bit wide two-way DRAM memory structure. In
fact, any number of 82353s can be used in parallel to implement busses
in 16-bit multiples.
The DRAM memory structure is very flexible allowing the designer to
achieve the desired price/performance objectives. DRAM SIMMs of 64K,
256K, 1M, and 4M in address depth and speeds of 60, 70, 80, or 100 ns
are supported in a "mix and match" arrangement, allowing memory
expansion without discarding different size or speed memory devices.
****82357 Integrated System Peripheral (ISP)...
****82358DT EISA Bus Controller...
****82359 DRAM Controller...
****82355 Bus Master Interface Controller (BMIC)...
***Configurations:...
***Features:...
**82420TX/ZX PCIset (for 486) TX (Saturn), ZX (Saturn II) c:Nov92...
**82420EX PCIset (for 486) EX (Aries) (82425EX/82426EX) <Dec94...
**82430LX PCIset (Pentium) LX (Mercury) (82433LX/82434LX) 03/22/93...
**82430NX PCIset (Pentium) NX (Neptune) (82433NX/82434NX) Mar94...
**82430FX PCIset (Pentium) FX (Triton I) (82437FX/82438FX)01/31/95...
**82430MX PCIset (Pentium) MX (Mobile Triton)(82437/438MX)11/01/95...
**82430HX PCIset (Pentium) HX (Triton II) (82439HX) 02/12/96...
**82430VX PCIset (Pentium) VX (Triton II) (82437VX/82438) 02/12/96...
**82430TX PCIset (Pentium) TX (Triton II) (82439TX) 02/17/97...
**82450KX/GX PCIset (Pentium Pro) KX/GX (Mars/Orion) 11/01/95...
**
**Support Chips:
**82091AA Advanced Interface Peripheral (AIP) c93...
**8289 Bus Arbiter (808x) c79...
**82289 Bus Arbiter for iAPX 286 Processor Family c83...
**82258 Advanced Direct Memory Access Coprocessor(ADMA) 01/01/84...
**82335 High-Integration Interface Device For 386SX c:Nov88...
**82360SL I/O Subsystem 10/05/90...
**82370 Integrated System Peripheral (for 82376) c:Oct88...
**82371FB/SB PCI ISA IDE Xcelerator 82371FB/82371SB (PIIX/3) 01/31/95...
**82371MX Mobile PCI I/O IDE Xcelerator (MPIIX) 11/01/95...
**82371AB PCI-TO-ISA / IDE Xcelerator 82371AB (PIIX4) 02/17/97...
**82374/82375 PCI-EISA Bridge (82374EB/82375EB, 374SB/375SB) c:Mar93...
**82378 System I/O (SIO) (82378IB and 82378ZB) c:Mar93...
**82379AB System I/O-APIC (SIO.A) <Dec94...
**82380 32-bit DMA Controller w/ Integrated Peripherals 02/01/87...
**82380FB/AB PCIset: 82380FB Mobile PCI-to-PCI Bridge(MPCI2) 02/17/97...
**82384 Clock Generator and Reset Interface c86...
**82385 32-bit Cache Controller for 80386 09/29/87...
**82385SX 32-bit Cache Controller for 80386SX 01/25/89...
**82395DX High Performance Smart Cache 06/18/90...
**82395SX Smart Cache 12/17/90
***Notes:...
**82396SX Smart Cache 12/17/90...
**82485 Turbo Cache (and 485Turbocache) c90...
**82489DX Advanced Programmable Interrupt Controller 10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
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