[Home] [This version is outdated, a new version is here]
*Title...
*Search:...
*Read Me/FAQ/General Info...
**Quote style:
To avoid thousands of quote marks and colliding with quote marks in
the text, I have used a modified quotation style. Anything in a
section titled "Info:" or "Features:" is a quote from a datasheet
unless otherwised stated in that section. In these sections anything
inside [] is an annotation and not part of the datasheet unless
otherwise stated in that section.
Under any other section, the text is my own unless indicated with "".
Also this document does not contain the entire datasheet for each
chip, usually only the first few pages are included to give an outline
of it. Some datasheets are 100s of pages other are only 1.
**Cant find a chip?...
**Why this document is not GPL or a wiki...
**Definition of a chip set:
In short it is a set of chips that allow a system designer to build a
computer. If we restrict the term 'chip' to that of a microchip then
technically any microcomputer contains a chip set, even one based of
7400-series logic alone.
In the context of this document, a chip set is defined as any group of
chips used to implement an IBM or IBM-compatible PC/XT/AT/386/486/etc
system.
There are 2 main categories that these chips fall into:
1. Direct copies or re-implementations of Intel chips
2. Chip sets sold as a set of chips to implement an IBM-compatible
that differ in some way to those used in an IBM system, e.g. not
pin compatible.
An example of the former would be some early chips built by VLSI
Technology (at the time known as VTI, to implement a 286:
o VL82C37A is a: 82C37A DMA controller
o VL82C59A is a: 82C59A interrupt controller
o VL82C54A is a: 82C54 timer
o VL82C612 is a: 74LS612 memory mapper
o VL82C84A is a: 82284 clock generator and ready interface
o VL82C88 is a: 82288 bus controller
These are all direct replacements for the parts used in an IBM AT.
Many companies had compatible versions of these chips.
An early example of the latter is the Chips & Technology NEAT chip set:
o 82C211 CPU/Bus controller,
o 82C212 Page/Interleave and EMS Memory controller,
o 82C215 Data/Address buffer
o 82C206 Integrated Peripherals Controller (IPC).
The description does not map directly to the parts used in the IBM AT.
Later chip sets are often even more integrated sometimes consisting of
just one chip, although two seems to be the most common.
The latter is generally considered the definition of a chip set, and
the former is not generally considered a chip set per-se. However when
looking at the early chip sets this distinction can be very
slight. Because of this, sets of chips meeting the criteria for (1.)
have been included where possible.
**'chip set', 'chip-set' or 'chipset'?...
**What's not included:...
**Who made the first chip set?...
**Spelling errors/mistyped words...
**Info needed on:...
**A note on VESA support of 486 chipsets....
**Datasheets:...
*_IBM...
*ACC Micro...
*ALD...
*ALi...
*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
*Contaq . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82395SX Smart Cache 12/17/90
***Notes:...
**82396SX Smart Cache 12/17/90...
**82485 Turbo Cache (and 485Turbocache) c90...
**82489DX Advanced Programmable Interrupt Controller 10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
**82C281/282 Cache Sx/AT (386SX) <08/22/91
***Notes:...
***Info:...
***Configurations:...
***Features:
o Flexible DRAM Banks Configuration
- The 82C281/2 supports 256K, 1M, and 4M memory devices, total
main memory size can be up to 16MB. A total of 12 different
memory configurations are supported.
o Page Mode Operation
- Based on the memory configuration shown above [see datasheet],
the memory control unit inside the 820281/2 performs page mode
of operation with a varying block size of 1k, 2k, or 4k bytes
for 256k, 1M, or 4M DRAMs respectively.
o System BIOS Shadow RAM
- The 820281/2 memory control unit provides shadow RAM feature for
several areas of memory system BIOS, video BIOS, and adapter
BIOS.
o Memory Remapping
- If shadow RAM feature is not utilized for the memory area
between 0D0000H - 0EFFFFH, then memory remapping is possible.
The local DRAM areas, 0A0000H - 0BFFFFH and 0D0000H - 0EFFFFH, a
total of 256 KByte, are remapped to the top of total system
memory. The areas for 0F0000H-0FFFFFH (system BIOS) and
0C000H-0CFFFFH (Video BIOS) are reserved for shadow RAM purpose.
o Flexible Multiplexed DRAM Address
o Cache Control Subsystem
- Direct-mapped posted write cache control function provides a low
cost alternative to enhance the system performance by up to 50%.
In order to simplify the design without increasing the system
cost or decreasing performance, the 82C281/2 has been designed
to support only non-pipeline mode for systems with cache memory.
The 82C281/2 offers the following cache control features:
- Flexible Cache Memory Size
- 4MB Cacheabie main memory by using 16KB low cost SRAM.
- 8MB Cacheable main memory by using 32KB low cost SRAM.
- Cache 16MB main memory by using 64KB low cost SRAM.
- Increase the cache size beyond 64KB up to 512KB
- Cache Line Size 4 Byte
- Burst mode memory prefetch is supported by the 82C281/2.
During cache read miss cycles, the memory control subsystem
will perform two consecutive read cycles to fetch 4 bytes
from main memory before terminating the cycle by sending
RDYO# signal to 3868X.
- Non-Cacheable Area
The non-cacheable areas are predefined as indicated below:
- I/O address space
- memory address between 0A0000H and 0FFFFFH.
- any memory address beyond the current configured memory
size.
- programmable non-cacheable memory area as defined by
82C281/2 internal registers.
- 82C281 Posted Write Cache
- The 820281 supports flexible direct-mapped cache with posted
write through update of main memory. By programming the
internal register, the post write control signals are
provided by the 820281 to support a one level write buffer.
With posted write, the CPU write cycles can be completed in
2 CPU T-States, thereby increasing system performance.
- 820282 Write Through Cache
- The 820282 supports a write-through cache system which
allows the designer to reduce system cost by eliminating two
F244's and two F373‘s with only a slight reduction in system
performance (5-10%).
- AT Bus Control
- The 820281/2 AT bus control unit handles all of the AT bus
operations and the DMA/Refresh arbitration. The AT bus
control unit supports the following features:
- Programmable AT Bus Clock - The AT bus clock, ATCLK. can
be programmed as CLK2/6, which is default, or CLK2/4.
- Turbo Switch - The 820281/2 provides a turbo switch
feature that allows users to change the system clock
speed. A programmable bit will enable or disable this
turbo function. When the turbo function is enabled by
setting reg[14H], bit[1] to 1, the 82C281/2 turbo pin
then determines the system clock speed. A low on the
turbo pin forces the CPU to run at the current AT bus
speed which IS CLK2/6 or CLK2/4.
**82C283 386SX System Controller c:91...
**82C291 SXWB PC/AT Chipset (386SX) c:91...
**82C295 SLCWB PC/AT Chipset (386SX) ?...
**82C381/382 HiD/386 (386DX) c:89...
**82C391/392 386WB PC/AT Chipset (386DX) <Dec90...
**82C461/462 Notebook PC/AT chipset [no datasheet] ?...
**82c463 SCNB Single Ship Notebook c:92...
**82c465MV/A/B Single-Chip Mixed Voltage Notebook Solution <Oct97...
**82C481?/482? HiP/486 & HiB/486 [no datasheet] Oct89...
**82C491/392 486WB PC/AT Chipset <04/21/91...
**82C493/392 486SXWB <10/21/91...
**82C495SX/392SX LCWB PC/AT chipset [no datasheet] ?...
**82C495SLC DXSLC 386/486 Low Cost Write Back c:92...
**82C495XLC PC/AT Chip Set c:93...
**82c496A/B DXBB PC/AT Chipset <Mar92...
**82C496/7 DXBB PC/AT Chipset (Cached) <01/16/92...
**82C498 DXWB PC/AT chipset [no datasheet] ?...
**82C499 DXSC DX System Controller c:93...
**82C546/547 Python PTM3V c:94...
**82C556/7/8 Viper [no datasheet] ?...
**82C556/7/8N Viper-N Viper Notebook Chipset <05/25/95...
**82C556M/7M/8E Viper-N+ Viper Notebook Chipset c:96...
**82C566/7/8 Viper-Max Chipset Scalable MultiMedia PC Solution ?...
**82C571/572 486/Pentium c:93...
**82C576/7/8 Viper Xpress [no datasheet] ?...
**82C576/8/9 Viper XPress+ [no datasheet, some info] <01/16/97...
**82C596/597 PTMAWB Pentium Adaptive Write-back (Cobra) c:93...
**82C650/1/2 Discovery (Pentium Pro) [no datasheet] ?...
**82C681/2/6/7 386/486WB EISA c:92...
**82C683 386/486AWB EISA [no datasheet] ?...
**82C693/6/7 Pentium uP Write Back Cache EISA c:93...
**82C700 FireStar c:97...
**82C701 FireStar Plus c:97...
**82C750 Vendetta [no datasheet] ?...
**82c801 SCWB2 DX Single Chip Solution c:92...
**82C802 SCWB2 PC/AT Single Chip [no datasheet] ?...
**82C802G/GP System/Power Management Controller (cached) c:93...
**82C895 System/Power Management Controller (cached) c:Sep94...
**82C898 System/Power Management Controller (non-cache)c:Nov94...
**
**Support Chips:
**82C601/2 Buffer Devices <Nov94...
**82C822 PCIB (VLB-to-PCI bridge) c:94...
**Other:...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...
(c) Copyright mR_Slugs Warehouse - All rights Reserved