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**Definition of a chip set:
In short it is a set of  chips that allow a system designer to build a
computer.  If we restrict the term  'chip' to that of a microchip then
technically any microcomputer  contains a chip set, even  one based of
7400-series logic alone.

In the context of this document, a chip set is defined as any group of
chips used to implement  an IBM or IBM-compatible PC/XT/AT/386/486/etc
system.

There are 2 main categories that these chips fall into:
1. Direct copies or re-implementations of Intel chips
2. Chip sets sold as a set of chips to implement an IBM-compatible 
   that differ in some way to those used in an IBM system, e.g. not 
   pin compatible.

An  example of  the former  would be  some early  chips built  by VLSI
Technology (at the time known as VTI, to implement a 286:
o  VL82C37A is a: 82C37A DMA controller
o  VL82C59A is a: 82C59A interrupt controller
o  VL82C54A is a: 82C54 timer
o  VL82C612 is a: 74LS612 memory mapper
o  VL82C84A is a: 82284 clock generator and ready interface
o  VL82C88  is a: 82288 bus controller

These are  all direct replacements  for the parts  used in an  IBM AT.
Many companies had compatible versions of these chips.

An early example of the latter is the Chips & Technology NEAT chip set:
o  82C211 CPU/Bus controller, 
o  82C212 Page/Interleave and EMS Memory controller, 
o  82C215 Data/Address buffer 
o  82C206 Integrated Peripherals Controller (IPC).

The description does not map directly to the parts used in the IBM AT.
Later chip sets are often even more integrated sometimes consisting of
just one chip, although two seems to be the most common.

The latter  is generally considered  the definition of a  chip set, and
the former is not generally  considered a chip set per-se. However when
looking  at   the  early  chip sets   this  distinction  can   be  very
slight. Because of this,  sets of chips  meeting the criteria  for (1.)
have been included where possible. 

**'chip set', 'chip-set' or 'chipset'?...
**What's not included:...
**Who made the first chip set?...
**Spelling errors/mistyped words...
**Info needed on:...
**A note on VESA support of 486 chipsets....
**Datasheets:...
*_IBM...
*ACC Micro...
*ALD...
*ALi...
*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
*Contaq  . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82395SX     Smart Cache                                     12/17/90
***Notes:...
**82396SX     Smart Cache                                     12/17/90...
**82485       Turbo Cache (and 485Turbocache)                      c90...
**82489DX       Advanced Programmable Interrupt Controller    10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set                           <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
**530/5595       (Sinbad) Host, PCI, 3D Graphics & Mem. Ctrl.<11/10/98
***Info:
The P5  A.G.P./VGA chipset, SiS530/5595, provides  a high performance/
cost index  Desktop/Mobile solution  for the Intel  Pentium P54C/P55C,
AMD K5/K6/K6-II, Cyrix M1/M2 and  other compatible Pentium CPU with 3D
A.G.P. VGA system.

The Host,  PCI, 3D A.G.P.  Video/Graphics & Memory  Controller, SiS530
integrates the  Host- to-PCI bridge,  the PCI interface, the  L2 cache
controller, the  DRAM controller, the high  performance hardware 2D/3D
VGA controller, and the PCI IDE controller.

The   Host  interface   supports   Synchronous/Asynchronous  Host/DRAM
clocking configuration to eminently improve the system performance and
DRAM compatibility issues.

The L2 cache controller can support up to 2 MB P.B. SRAM, and the DRAM
controller  can support  SDRAM  memory  up to  1.5  GBytes with  three
double-sided  SDRAM  DIMMs  configuration.  The cacheable  DRAM  sizes
support up to 256 MBytes.

The built-in fast PCI IDE controller supports the ATA PIO/DMA, and the
Ultra DMA33/66 function  that support the data transfer  rate up to 66
MB/s. It provides the separate data path for two IDE channels that can
eminently improve the performance under the multi-tasking environment.

The A.G.P. internal  interface is supported for integrated  H/W 3D VGA
controller. The  integrated VGA controller  is a high  performance and
targeted at  3D graphics application.  In addition,  the integrated 3D
Video/Graphics controller adopts the  64bits 100MHz host bus interface
high  technology  to  improve  the performance  eminently.   To  cost-
effective the PC system, the  share system memory architecture will be
adopted and  it can flexibly using  the 2MB, 4MB and  8MB frame buffer
size  from programming  the system  BIOS. [something  got  confused in
translation  there  didn't it?]  To  enhance  the system  performance,
SiS530 also supports the local  frame buffer solution and memory sizes
can support up to 8MB with SDRAM and SGRAM.

In addition  to provide  the standard interface  for CRT  monitors, it
also  provides  the Digital  Flat  Panel  Port  (DFP) for  a  standard
interface  between  a  personal  computer  and a  digital  flat  panel
monitor. This  port allows a host  computer to connect  directly to an
external  flat panel  monitor without  the need  for analog-to-digital
conversion  found  in most  flat  panel  monitors  today. As  for  DVD
solution,  the  integrated 3D  VGA  controller  also  support DVD  H/W
accelerator to improve the DVD playback performance.

The SiS5595 PCI  system I/O integrates the PCI-to-ISA  bridge with the
DDMA, PC/PCI DMA  and Serial IRQ capability, the  ACPI/Legacy PMU, the
Data  Acquisition   Interface,  the  Universal   Serial  Bus  host/hub
interface,  and the  ISA  bus  interface which  contains  the ISA  bus
controller, the DMA controllers, the interrupt controllers, the Timers
and  the  Real Time  Clock  (RTC).  It  also integrates  the  Keyboard
Controller and PS/2 mouse interface that can support keyboard power on
function  for users  to power  on system  by entering  the hot  key or
password from  keyboard. The built-in  USB controller, which  is fully
compliant to  OHCI (Open Host Controller Interface),  provides two USB
ports  capable  of  running  full/low  speed USB  devices.   The  Data
Acquisition Interface  offers the ability of  monitoring and reporting
the environmental  condition of  the PC. It  could monitor  5 positive
analog voltage inputs, 2 Fan speed inputs, and one temperature input.

In  addition, SiS5595  also supports  ACPI function  to  meet Advanced
Configuration and Power Interface (ACPI) 1.0 specification for Windows
98 environment,  it can support power-management  timer, Power button,
Real-time  clock alarm  wake up,  more  sleeping state,  ACPI LED  for
sleeping and  working state, LAN wake  up, Modem Ring In  wake up, and
OnNow initiative function.

***Configurations:...
***Features:...
**540            (Spartan) Super7 2D/3D Ultra-AGP Single C.S.<11/30/99...
**55x            SoC (System-on-chip)                        <03/14/02...
**
**Support chips:
**85C206     Integrated Peripheral Controller [no datasheet]         ?...
**5595       Pentium PCI System I/O                          <12/24/97...
**950        LPC I/O                                         <07/16/99...
**Other:...
**PII/III/Pro...
**Athlon etc...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...

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