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**?????  (Profusion)    c:99
Chips:         
Memory Access Controller (MAC)  
Data Interface Buffer (DIB)
CPUs:          8x P-III Xeon Oct
DRAM Types:    SDRAM PC100 2-way Interleave dual channel
Max Mem:       32GB
ECC/Parity:    ECC
AGP speed:     N/A
Bus Speed:     100
PCI Clock/Bus: 1/3 PCI-66/64



**800 series...
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*Unresearched:...
*VIA...
*VLSI...
**VL82C316         SCAMP II, PC/AT-Compatible System Controller      ?
***Info:...
***Configurations:...
***Features:...
**VL82C323         SCAMP II, 5 Volt Power Management Unit (PMU)      ?...
**VL82C380         Single chip 386DX PC/AT Controller +on-chip cache ?...
**VL82C325             VL82C386SX System Cache controller            ?...
**VL82C335             VL82C386DX System Cache ctrl. [no d.sheet]    ?...
**VL82C315A/322A/3216  Kodiak 32-Bit Low-Voltage Chip Set            ?...
**VL82C420/144/146     SCAMP IV [no datasheet, some info]          c93...
**VL82C480         System/Cache/ISA bus Controller                   ?...
**VL82C481         System/Cache/ISA bus Controller                 c92
***Basics:...
***Info:...
***differences to the VL82C480:
"It  also  supports  486  family   CPUs  that  contain  an  integrated
write-back cache (P24T, etc.)"

"It can also  perform 3-2-2-2 cycle reads for support  of slower SRAMs
at higher frequences."

"The HITM#  input is provided to  force the VL82C481 to  abort DRAM or
cache cycles when a hit on a dirty line in the CPU write-back cache is
detected. the DRAM or cache  cycle is subsequently restarted after the
CPU has written back the dirty data"

"Further support for devices that reside  on the local bus is provided
through use of the <*LDEV#*> (Local Bus Access) input, which deselects
the VL82C481 during  CPU cycles <*and causes the  VL82C481 to generate
VL-Bus  memory  cycles  when  active  dur- ing  DMA  and  Master  Mode
cycles*>."

[areas  marked <*  *> are  differences or  additions, in  the VL82C480
LDEV# is LBA#]

<*On power-on  default,*> The  chip does not  generate parity  for CPU
writes to DRAM, but does  generate cache write-back cycles. <*However,
a mode is  provided in which the VL82C481 will  generate parity during
either CPU writes or VL master writes.*>

[areas marked <* *> are additions]

***Configurations:...
***Features:...
**VL82C486         Single-Chip 486, SC486, Controller                ?...
**VL82C425         486 Cache controller                              ?...
**????????         Cheetah 486, PCI [no datasheet]                   ?...
**VL82C3216        Bus Expanding Controller Cache with write buffer  ?...
**VL82C521/522     Lynx/M                                            ?...
**VL82C530         Eagle Ð                                         c95...
**VL82C541/543     Lynx                                            c95...
**VL82C591/593     SuperCore 590                                   c94...
**VL82C594/596/597 Wildcat                                         c95...
**I/O Chips:
**VL82C106 Combination I/O chip                                      ?...
**VL82C107 SCAMP  Combination I/O chip                               ?...
**VL82C108 TOPCAT Combination I/O chip                               ?...
**VL82C110 Combination I/O chip                                      ?...
**VL82C113 SCAMP  Combination I/O chip                               ?...
**VL82C114 Combination I/O chip                                      ?...
**Video: ...
**Disk:...
**Modems:...
**Other:...
**Not sure if they actually exist...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...