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M2228 Video
M2301 Video
M2302 Video
M2308 Video
M2401 Video
M3125 Video
M3135 Video (super VGA)
M3143 Video
M3145 PCI Video
M3145 VLB/PCI 3D Video
M3147V PCI Video
M3149 Video
M3151 PCI 3D Video, 4MB MAX
M3307 MPEG Video Decoder Chip
M3309 MPEG-II Video Decoder Chip
M3321 MPEG-II A/V Decoder Chip
M3351 MPEG-II Video Decoder Chip
M4803 PCI EIDE Controller
M5105 VLB Super I/O Controller FDD/HDD/LPT/2xCOM/GAME
M5113 Superset of 5105, with PnP, ECP/EPP LPT and IR port
M5119 Super I/O
M5123 Super I/O PnP/2xCOM/IR port/Keyboard (For Phoenix BIOS)
M5125 same as M5123 but for AMI
M513? Super I/O PnP/Keyboard
M5135F Super I/O PnP/Keyboard/IR
M514? Super I/O PnP/Keyboard/IR/2xCOM/
M5213 PCI IDE
M5217/H Super I/O
M5219 PCI? Bus mastering EIDE
M5225 PCI? EIDE
M5229 PCI? Bus mastering EIDE
M5235 Super I/O
M5237 PCI USB Host
M5240 PCI? EIDE
M5241 PCMCIA Bridge
M5242 ?
M5244 FDD
M5427 PCI-AGP Bridge
M5451 Audio
M5453 Modem
M5455 Audio
*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
*Contaq . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
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*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94
***Notes:...
***Info:...
***Configurations:...
***Features:
o High Performance Second Level Cache
- Zero Wait States at 66 MHz
- Two-Way Set Associative
- Writeback with MESI Protocol
- Concurrent CPU Bus and Memory Bus Operation
- Boundary Scan
o Pentium Processor (735\90, 815\100)
- Chip Set Version of Pentium Processor (735\90, 815\100)
- Superscalar Architecture
- Enhanced Floating Point
- On-Chip 8K Code and 8K Data Caches
- See Pentium Processor Family Data Book for More Information
o Highly Flexible
- 1 Mbyte to 2 Mbyte
- 64-, or 128-Bit Wide Memory Bus
- Synchronous, Asynchronous and Strobed Memory Bus Operation
- Selectable Bus Widths, Line Sizes, Transfers and Burst Orders
o Full Multiprocessing Support
- Concurrent CPU, Memory Bus and Snoop Operations
- Complete MESI Protocol
- Internal/External Parity Generation/Checking
- Supports Read For Ownership, Write-Allocation and Cache-to-Cache
Transfers
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:
Chips:
[82454NX] (PXB) [82453NX] (MUX)
[82452NX] (RCG) [82451NX] (MIOC)
[82371EB] (PIIX4E),
CPUs: Single/Dual/Quad P-II Xeon/P-III Xeon
DRAM Types: FPM EDO 2-way Interleave 4-way Interleave
Mem Rows: 8
DRAM Density: 16Mbit 64Mbit
Max Mem: 8GB
ECC/Parity: Both
AGP speed: N/A
Bus Speed: 100
PCI Clock/Bus: 1/3
**????? (Profusion) c:99...
**800 series...
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