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**?????  (Profusion)    c:99
Chips:         
Memory Access Controller (MAC)  
Data Interface Buffer (DIB)
CPUs:          8x P-III Xeon Oct
DRAM Types:    SDRAM PC100 2-way Interleave dual channel
Max Mem:       32GB
ECC/Parity:    ECC
AGP speed:     N/A
Bus Speed:     100
PCI Clock/Bus: 1/3 PCI-66/64



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*Unresearched:...
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*VLSI...
**VL82C480         System/Cache/ISA bus Controller                   ?
***Info:
The   VL82C480   controller   is   designed  to   control   486DX   or
486SX/487SX-based  ISA bus  systems  operating  at up  to  40 MHz.  It
replaces the following devices on the motherboard:
o  Two 82C37A DMA controllers
o  Two 82C59A interrupt controllers
o  82C54 timer
o  74LS612 memory mapper
o  82284 clock generator and ready interface
o  82288 bus controller

The following controller blocks are also included on-chip:
o  Memory/refresh controller
o  Port B and NMI logic
o  Bus steering logic
o  Turbo Mode control logic
o  Parity checking logic
o  Parity generation logic
o  Writ-back look-aside cache controller

The VL82C480 supports the Weitek 4167 Numeric Coprocessor.

The memory controller logic is capable of accessing up to 64 MB. there
can be up to four banks of 256K, 1M, or 4M DRAMs used in a system. The
VL82C480 can drive two banks without external buffering. Built-in Page
Mode operation and  up to two-way interleaving allows  the PC designer
to maximize  system perform-  ance using low-cost  DRAMs. Programmable
DRAM timing  is provided for  RAS# pre- charge, RAs-to-CAS  delay, and
CAS# pulse width.

The VL82C480  write-back cache  controller logic  supports one  or two
bank direct map write-back cache  with external tag storage. The cache
controller can per- form 2-1-1-1 reads with two banks or 2-2-2-2 reads
with  one bank.  The VL82C480  can perform  one wait  state writes  on
cache-hits. An optional zero wait state write mode is provided for use
with fast cache SRAMs. The cachable DRAM  range includes 2 MB up to 64
MB  utilizing  cache   data  SRAM  sizes  of  32  KB   through  1  MB,
respectively.

Shadowing features are  supported on 16K boundarys  between A0000h and
FFFFFh (640 KB  to 1 MB). simultaneous use of  shadowed ROM and direct
system board  access is possible  in a non-overlapping  fashion throu-
ghout this memory space. Control over four access options is provided:
1. Access ROM or slot bus for reads and writes.
2. Access system board DRAM for reads and writes.
3. Access system board DRAM for reads and slot bus for writes.
4. Shadow setup mode. Read ROM of slot bus, write system board DRAM.

Three special programmable address regions  are provided. the Fast Bus
Clock Reg- ion  allows accesses to certain memory regions  at a faster
ISA  bus  clock  rate  for   fat  on-board  or  off-board  devices.  A
Non-Cacheable Region and/or a Write-Pro-  tected Region may be defined
by a set of six registers that allow  memory in the region 640 KB to 1
MB to be marked as  non-cacheable and/or write-protected in increments
of 16 KB. A further set of registers allows a memory range anywhere in
the first 64  MB of memory to be  marked as a DRAM region,  an ISA bus
region, or  a local  bus region, either  cachable or  non-cacheable in
increments of 2 KB. 64 KB, or 1 MB.

further support for  devices that reside on the local  bus is provided
through use of the LBA# (Local  Bus Access) input, which deselects the
VL82C480 during CPU cycles. Also, a memory range anywhere in the first
64 MB of memory can be pro- grammed via the internal mapping registers
to make  the VL82C480 access  a local bus device  as a CPU  bus memory
device  during  DMA or  Master  Mode  transfers,  and de-  select  the
VL82C480 during CPU cycles.

The VL82C480 handles  system board refresh directly  ans also controls
the  timing  of  slot  bus   refresh.  Refresh  may  be  performed  in
synchronous,  Asynchronous or  De-  coupled Mode.  In the  Synchronous
Mode, slot bus and on-board DRAM refresh cycles proceed simultaneously
with  all   memory  cycles  held   until  both  have   completed.  The
Asynchronous Mode allows  in- and off-board refreshes  to be initiated
sumultane-  ously, but  to complete  asynchronously, allowing  earlier
access to DRAM.  In the Decoupled Mode, a separate  refresh counter is
used for slot bus refresh, allowing on-board DRAM and system refreshes
to  proceed independently,  with DRAM  refreshes initiated  during bus
idle cycles. CAS-before-RAS refresh is also supported. Re- freshes are
staggered to minimize power supply  loading and attenuate noise on the
VDD and VSS  pins. The VL82C480 supports the ISA  bus standard refresh
period of 15.625 us as well as 125 us.

The interrupt controller  logic consists of two  82C50A megacells with
eight inter- rupt  request lines each. The two  megacells are cascaded
internally and three of the  interrupt request inputs are connected to
internal circuitry, sa a total  of 13 external interrupt request lines
are  available.  these  13  interrupt request  lines  plus the  Weitek
interrupt request  line, the  ten-channel check  line, and  the Turbo/
Non-Turbo line  are scanned in  through one  pin on the  VL82C480. Two
external 74LS166s are required for scanning in these 16 signals.

The  interval timer  includes  one 82C54  counter/timer megacell.  the
counter/timer   has  three   independent  16-bit   counters  and   six
programmable counter modes.

The  two DMA  controllers are  82C37A compatible.  Each controls  data
transfers bet-  ween an I/O channel  and on- or off-board  memory. The
DMA  controllers  can  transfer  data   over  the  full  64  MB  range
available. Internal  latches are  provided for  latc- hing  the middle
address  bits output  by the  82C37A megacells  on the  data bus.  The
74LS612 memory  mappers are integrated  to generate the  upper address
bits.

The  VL82C480  can  be  programmed  for  asynchronous  or  synchronous
operation of the ISA bus.

The  VL82C480 also  performs  all the  data  buffer control  functions
required for a 486-based ISA bus system. Under the control of the CPU,
the VL82C480 routes data to and from  the CPU's D bus, the internal XD
bus, and  the slots (SD  bus). During CPU ISA  bus reads, the  data is
latched for synchronization with the CPU.  Parity is checked for D bus
DRAM read operations. The chip does not generate parity for CPU writes
to DRAM,  but does  generate cache write-back  cycles. Even  parity is
gen- erated and checked.

***Configurations:...
***Features:...
**VL82C481         System/Cache/ISA bus Controller                 c92...
**VL82C486         Single-Chip 486, SC486, Controller                ?...
**VL82C425         486 Cache controller                              ?...
**????????         Cheetah 486, PCI [no datasheet]                   ?...
**VL82C3216        Bus Expanding Controller Cache with write buffer  ?...
**VL82C521/522     Lynx/M                                            ?...
**VL82C530         Eagle Ð                                         c95...
**VL82C541/543     Lynx                                            c95...
**VL82C591/593     SuperCore 590                                   c94...
**VL82C594/596/597 Wildcat                                         c95...
**I/O Chips:
**VL82C106 Combination I/O chip                                      ?...
**VL82C107 SCAMP  Combination I/O chip                               ?...
**VL82C108 TOPCAT Combination I/O chip                               ?...
**VL82C110 Combination I/O chip                                      ?...
**VL82C113 SCAMP  Combination I/O chip                               ?...
**VL82C114 Combination I/O chip                                      ?...
**Video: ...
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**Other:...
**Not sure if they actually exist...
*Western Digital...
*Winbond...
*ZyMOS...
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