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**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93
***Notes:
Date source: TimelineDateSort7_05.pdf

Information taken from: 
            1995_Intel_Pentium_Processors_and_Related_Components.pdf*
                                         8249x Cache controllers.pdf**

>*  Datasheet dated Oct'93
>** Datasheet undated, whole document dated '95

The info and features section have  been solely sourced from the first
source.   The  second source  provides  far  more detail.   Additional
information in  the configurations section  has been sourced  from the
second.

This  chip was  used on  the Pentium  66MHz CPU  complexes of  Intel's
Xpress platform.   Specifically the  BXCPUPENT66 (Single  66MHz, eight
82491s) and BXCPU2XPENT (Dual 66 MHz,  eight 82491s). Also found on P5
60/66MHz CPU complexes of IBM 9595/PC Server 300/500 systems.

***Info:...
***Configurations:...
***Features:...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
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**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
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**WD8110        System controller for 80386DX/486            <11/30/93
***Notes:...
***Info:...
***Configurations:...
***Features:
o   Interfaces with 80486SX, 80486SXLP, 80486DX, 80386SX and 80386DX
    CPU's
o   Operates at up to 33 MHz at 3.3 volts or 5 volts with the 
    80486SX/DX
o   Operates at up to 33 MHz with the 80386SX/DX
o   Supports single and double clock 80486SX/DX and Intel SL Enhanced 
    processors.

DRAM control:
o   Page Mode word interleaved, DRAM controller with support for 80486
    burst mode.
o   Supports 3-2-2-2 clock sequence, 9 CLKs with 16-byte line fill for
    a page hit DRAM read cycle at 33 MHz.
o   Optional 3-1-1-1 clock sequence, 6 CLKs with 16-byte line fill for
    static column mode DRAMs at CPU speeds of 16 MHz and 20 MHz
o   Zero Wait State writes at 16 MHz and 20 MHz to DRAMS for 
    80486SX/DX
o   One Wait State writes to DRAMs for 80386SX/DX
o   One Wait State reads from DRAMs for Page Hit access for 80386SX/DX
o   Supports memory in five DRAM banks for a maximum of 256 Mbytes,
    using 256Kbit, 1 Mbit, 4 Mbit and 16 Mbit DRAMs and special DRAMs 
    such as 512K by 9, 1M by 18 and 2M by 9.
o   Supports major DRAM standards, including Asymmetrical DRAMs Static 
    Column DRAMs and 88-pin DRAM cards.
o   Self-adjusting output drivers minimize output rise/fall time 
    variations and reduce EMI and ground noise.
o   DRAM address multiplexer capable of driving 450 pF with adjustable
    strength drivers.
o   Features CAS before RAS refresh and slow refresh for low power.
o   Supports slow refresh and self refresh DRAMs at 120 us.
o   I/O mapping for board testability
o   32-bit direct interface with internal parity generation and 
    checking with no DRAM data buffers required.

Power Management:
o   Low power 0.9 micron CMOS technology
o   Provides power control with suspend and resume mode operations.
o   3 volt suspend to hard disk and Hibernation.
o   Sleep Mode provides:
    - Stop clock for static CPU for power saving.
    - Processor power down.
o   Provides automatic processor clock switching for 80386.
o   Automatic CPU speedup (AutoFast).
    - Clock Scaling
    - Clock Throttling
o   Supports multiple CPU speeds.
o   Supports System Management Interrupt (SMI) for efficient power 
    management.
o   Provides peripheral and I/O power control with trapping on I/O 
    address ranges for SMI operations.
o   Supports a fully programmable 16-bit decode.
o   Provides System Activity Monitor (SAM) for power management.
o   Stop DMA clock.
o   3.3V low voltage operation with on-chip translators for 5 volt AT 
    bus 
    (split rail operation).
o   3 volt and 5 volt mixed mode.

Chip Set Features:
o   High speed DMA.
o   Three fully programmable chip selects with PMC timers.
o   Built in Immunizer for virus protection.
o   Connects directly to the AT Data Bus SD(15:00).
o   Supports a Video Local Bus Interface (VLBI) for a 32-bit Video 
    Graphic Array (VGA) interface.
o   Bank switched BIOS ROM up to 512 KB.

**
**Support Chips:
**WD76C20x   Floppy, RTC, IDE and Support Logic Device       <11/25/91...
**WD76C30x   Perip. Ctrl, Interrupt Multiplex, and Clock Gen <11/18/91...
**WD7615     Desktop Buffer Manager                          <04/15/92...
**WD7625     Desktop Buffer Manager                          <10/01/92...
**WD8120LV   Super I/O [no datasheet]                                ?
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