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**82485 Turbo Cache (and 485Turbocache) c90
***Notes:...
***Info:...
***Versions:...
***Features:...
**82489DX Advanced Programmable Interrupt Controller 10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
**800 series...
*Headland/G2...
**GCK113 80386 AT Compatible Chip Set c:oct89
***Info:
The GCK131 Chip Set, of three highly integrated HCMOS microchips,
supports an 80386 microprocessor-based computer system in AT-compat-
ible mode at speeds up to 25 MHz.
This high performance three chip set allows the implementation of a
powerful computer system with just these components: an 80386
Microprocessor, a keyboard controller, a real time clock, six bipolar
devices and up to 24 Mb of memory.
System configuration data is stored in an external EEPROM to eliminate
the need for DIP switches and jumpers. Register data for memory and
I/O wait states, command delays, and recovery times can be con-
veniently programmed for the system user through software.
The chip set, using interleaving and page mode access techniques,
supports six banks of 32-bit RAM. System BIOS and video BIOS can be
'shadowed' to RAM for faster operation. And ROM accesses can be con-
figured to as low as 1 wait state for optimum performance.
GC131 Peripheral Controller
This single chip effectively replaces two 8259, two 8237, 8254 , an
LS612, and other devices. The chip interfaces with an 8042 keyboard
controller, real time clock, parallel ports, serial ports, speaker and
the EEPROM used for power up configuration.
GC132 CPU/Memory Controller
This powerful chip decodes the processor address and control lines and
generates the RAS , CAS, and chip select signals required for memory
management. Both static and dynamic memories can be used. The GC132
Controller features both paged and interleaved memory access techni-
ques that improve overall system throughput.
GC133 Bus Bridge Interface
[no text]
***Configurations:...
***Features:...
**GCK181 Universal PS/2 Chip Set c:Mar89
***Info:...
***Configurations:...
***Features:...
**HT11 Single 286 AT Chip [no datasheet] <Aug90...
**HT12/+/A Single 286 AT Chip with EMS support c:Aug90...
**HT18 80386SX Single Chip c:Sep91...
**HT21 386SX/286 Single Chip (20 MHz) c:Aug91...
**HT22 386SX/286 Single Chip (25 MHz) c:Sep91...
**HT25 3-volt Core Logic for 386SX c:Dec92...
**HT35 Single-Chip Peripheral Controller [partial info] ?...
**HTK320 386DX Chip Set c:Sep91...
**HTK340 "Shasta" 486 Chip Set c:Jun92...
**Support Chips:
**HT44 Secondary Cache c:Jun92...
**Other:...
*HMC (Hulon Microelectronics)...
*Logicstar...
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