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**Intro:
The information  contained within this  file should not  be considered
100%  correct.   Where  possible   information  has  been  taken  from
datasheets, however  even this info  may be incorrect.  The datasheets
state what  the chip should  do, not what  they actually do.  This is,
compounded further by different revisions of chips.

This  document will  never be  complete, and  I have  no intention  of
finding every  datasheet for  every chip  set. Some  of the  chip sets
listed are  from later systems  in the PIII/P4/Athlon era.   There are
many websites  with information on  these chip sets and  these entries
will likely not be expanded upon.  The focus of this document is early
PC/XT to  Pentium chip sets.  There are  few sites that  clearly illu-
strate this information, and how they relate to each other.

I  aim  to  prioritize   cataloging  significant,  rare  or  otherwise
interesting chip sets.

BTW the reason I wrote all of this down, is so that I could FORGET it.
Basically I needed to free  up some RAM.  I've  a head full  of arcane
snippets of  information on this subject.   I don't want to  end up  a
crazy old man  ranting random disjointed information  ("The C&T CS8220
came before the CS8221 you KNOW!") to disinterested passersby,  unable
to see how senile I've become. A side benefit, this might be useful to
someone else:-)

**Quote style:
To avoid  thousands of quote marks  and colliding with quote  marks in
the  text, I  have used  a modified  quotation style.   Anything in  a
section  titled "Info:"  or "Features:"  is a  quote from  a datasheet
unless otherwised stated in that  section.  In these sections anything
inside  [] is  an  annotation and  not part  of  the datasheet  unless
otherwise stated in that section.

Under any other section, the text is my own unless indicated with "".

Also  this document  does not  contain the  entire datasheet  for each
chip, usually only the first few pages are included to give an outline
of it. Some datasheets are 100s of pages other are only 1.

**Cant find a chip?...
**Why this document is not GPL or a wiki...
**Definition of a chip set:...
**'chip set', 'chip-set' or 'chipset'?...
**What's not included:...
**Who made the first chip set?...
**Spelling errors/mistyped words...
**Info needed on:...
**A note on VESA support of 486 chipsets....
**Datasheets:...
*_IBM...
*ACC Micro...
*ALD...
*ALi...
*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
*Contaq  . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91
***Notes:...
***Info:...
***Features:...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94
***Notes:...
***Info:
The 82498 Cache Controller and multiple 82493 Cache SRAMs combine with
the Pentium processor (735/90,  815/100) and future Pentium Processors
to form a CPU Cache chip set designed for high performance servers and
function-rich  desktops. The high-speed  interconnect between  the CPU
and  cache components has  been optimized  to provide  zero-wait state
operation. This CPU  Cache chip set is fully  compatible with existing
software,  and has new  data integrity  features for  mission critical
applications.

The 82498 Cache Controller implements the MESI write-back protocol for
full multiprocessing support.  Dual ported buffers and registers allow
the 82498  to concurrently  handle CPU bus,  memory bus,  and internal
cache operation for maximum performance.

The 82493 is a customized high-performance SRAM that supports 64-, and
128-bit  wide memory  bus widths,  32-,  and 64-byte  line sizes,  and
optional sectoring. The  data path between the CPU  bus and memory bus
is  separated  by  the  82493,  allowing  the  CPU  bus  to  handshake
synchronously,  asynchronously,  or   with  a  strobed  protocol,  and
allowing concurrent CPU bus and memory bus operations.

***Configurations:...
***Features:...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...