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**Quote style:
To avoid thousands of quote marks and colliding with quote marks in
the text, I have used a modified quotation style. Anything in a
section titled "Info:" or "Features:" is a quote from a datasheet
unless otherwised stated in that section. In these sections anything
inside [] is an annotation and not part of the datasheet unless
otherwise stated in that section.
Under any other section, the text is my own unless indicated with "".
Also this document does not contain the entire datasheet for each
chip, usually only the first few pages are included to give an outline
of it. Some datasheets are 100s of pages other are only 1.
**Cant find a chip?...
**Why this document is not GPL or a wiki...
**Definition of a chip set:...
**'chip set', 'chip-set' or 'chipset'?...
**What's not included:...
**Who made the first chip set?...
**Spelling errors/mistyped words...
**Info needed on:...
**A note on VESA support of 486 chipsets....
**Datasheets:...
*_IBM...
*ACC Micro...
*ALD...
*ALi...
*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
*Contaq . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**450NX (?) 06/29/98:
Chips:
[82454NX] (PXB) [82453NX] (MUX)
[82452NX] (RCG) [82451NX] (MIOC)
[82371EB] (PIIX4E),
CPUs: Single/Dual/Quad P-II Xeon/P-III Xeon
DRAM Types: FPM EDO 2-way Interleave 4-way Interleave
Mem Rows: 8
DRAM Density: 16Mbit 64Mbit
Max Mem: 8GB
ECC/Parity: Both
AGP speed: N/A
Bus Speed: 100
PCI Clock/Bus: 1/3
**????? (Profusion) c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
**82C596/597 PTMAWB Pentium Adaptive Write-back (Cobra) c:93
***Notes::...
***Info:...
***Configurations:...
***Features:
o 100% PC/AT compatible
o Fully supports the Intel Pentium microprocessor
o Three chip PC/AT solution: 82C596, 82C597 and 82C206
o Supports Intel Pentium CPU address pipelining
o IX clock source, supporting systems running up to 66 MHz
o Adaptive Write Back, direct-mapped cache with size
selections: 64K, 128K, 256K, 512K, 1Mb, 2Mb
o Programmable cache write policy: adaptive write back (AWB),
write-back or write through
o Fully programmable cache and DRAM read/write cycles
o Supports 3-2-2-2 cache burst read cycle at 66 MHz
o Built-in TAG auto-invalidation circuitry
o Support for two programmable non-cacheable/system memory "hole"
regions
o Supports two banks of 64-bit wide DRAMs with 256K,
512K, 1 M, 2M, 4M, and 8M x 36 page-mode DRAMs
o Supports DRAM configurations up to 128 Mb
o Supports 3-3-3-3 pipeline DRAM burst cycles
o DRAM post write buffer
o Provides Flash ROM support
o 33 MHz asynchronous 32-bit VESA VL Local Bus support
o Performance oriented snoop-line comparator for VL/ISA bus masters
o Extended DMA page register
o Asynchronous CPU and VL bus interface
o AT bus clock speed programmability
o Low power, high speed CMOS technology
**82C650/1/2 Discovery (Pentium Pro) [no datasheet] ?...
**82C681/2/6/7 386/486WB EISA c:92...
**82C683 386/486AWB EISA [no datasheet] ?...
**82C693/6/7 Pentium uP Write Back Cache EISA c:93...
**82C700 FireStar c:97...
**82C701 FireStar Plus c:97...
**82C750 Vendetta [no datasheet] ?...
**82c801 SCWB2 DX Single Chip Solution c:92...
**82C802 SCWB2 PC/AT Single Chip [no datasheet] ?...
**82C802G/GP System/Power Management Controller (cached) c:93...
**82C895 System/Power Management Controller (cached) c:Sep94...
**82C898 System/Power Management Controller (non-cache)c:Nov94...
**
**Support Chips:
**82C601/2 Buffer Devices <Nov94...
**82C822 PCIB (VLB-to-PCI bridge) c:94...
**Other:...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...
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