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**ET6000     "Cheetah" 486DX/SX Non-Cache System                <Apr92
***Info:...
***Configurations:...
***Features:
o   100% IBM PC/AT Compatible 1-Chip AT Solution
o   Designed to work at 16, 20, 25, 33 and 50MHz on a 4868X/DX based
    system
o   Fast Burst Mode Memory Manager - Burst Read and 0WS Write
o   One blocks of non-cacheable memory regions
o   Up to 64MB DRAM support with Page Mode
o   Mixing DRAM configurations - 256K, 1M and 4M devices
o   Single ROM BIOS
o   Shadow RAM option
o   Software Programmable DRAM Wait States
o   Fast Reset and Gate A20 to Optimize OS/2
o   Asynchronous AT Bus Clock Generation
o   Support Intel 80487SX and Weitek 4167 Coprocessor without external
    PALs
o   Concurrent Refresh and AT Refresh Option
o   Hardware and Software Turbo Clock Switching
o   Local Bus support
o   Less than 10 components plus memory to implement an unique 486
    system
o   1.0 Micron Low Power, High Speed CMOS Technology
o   160 Pin PQFP package

**ET9000     "Jaguar" 486 Write Back Cache AT Single Chip       <Jun92...
**ET9800/391 "Firefox" 386SX Write Back chipset [no datasheet]       ?...
**82C390SX   "Panda" S.C. 386SX Direct Mapped Cache [no d.sheet]cFeb92...
**66x8       VIA clones [no datasheet]                               ?...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82495DX/490DX DX CPU-Cache Chip Set                           <Sep91
***Notes:...
***Info:...
***Configurations:...
***Features:...
**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
**IBM AT: MC146818 Real Time Clock                                 <84
***Info:...
***Versions:...
***Features:
o   Low-Power, High-Speed, High-Density CMOS
o   Internal Time Base and Oscillator
o   Counts Seconds, Minutes, and Hours of the Day
o   Counts Days of the Week, Date, Month, and Year
o   3 V to 6 V Operation
o   Time Base Input Options: 4.194304 MHz, 1.048576 MHz, or 32,768 kHz
o   Time Base Oscillator for Parallel Resonant Crystals
o   40 to 200 uW Typical Operating Power at Low Frequency Time Base
o   4.0 to 20 mW Typical Operating Power at High Frequency Time Base
o   Binary or BCD Representation of Time, Calendar, and Alarm
o   12- or 24-Hour Clock with AM and PM in 12-Hour Mode
o   Daylight Savings Time Option
o   Automatic End of Month Recognition
o   Automatic Leap Year Compensation
o   Microprocessor Bus Compatible [this means absolutely nothing]
o   MOTEL Circuit for Bus Univerality
o   Multiplexed Bus for Pin Efficiency
o   Interfaced with Software as 64 RAM Locations
o   14 Bytes of Clock and Control Registers
o   50 Bytes of General Purpose RAM
o   Status Bit Indicates Data Integrity
o   Bus Compatible Interrupt Signals (IRQ)
o   Three Interrupts are Separately Software Maskable and Testable
      Time-of-Day Alarm, Once-per-Second to Once-per-Day
      Periodic Rates from 30.5 us to 500 ms
      End-of-Clock Update Cycle
o   Programmable Square-Wave Output Signal
o   Clock Output May Be Used as Microprocessor Clock Input
      At Time Base Frequency /1 or /4
o   24-Pin Dual-In-Line Package



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