[Home] [This version is outdated, a new version is here]
*Title...
*Search:...
*Read Me/FAQ/General Info...
**Datasheets:

See:
 http://108.59.254.117/~mR_Slug/pub/datasheets/chipsets/

Regetfully I did not keep them all.

*_IBM...
*ACC Micro...
*ALD...
*ALi...
*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
*Contaq  . . . . . [no datasheets, some info]...
**82C596/A  3/486 Writeback Cache [no datasheet]             <11/11/92
Possibly  two variant,  or one  version with  two names,  one  being a
shorthand:
82C596
82C596A

ftp://ami.com/archive/Other_Manuals/!index.txt
lists the A variant with the date 11/11/92. No date for non-A:
" 
CTQ596.Z06    	88900   12-21-92  3/486 Contaq 596 chipset    06-06 core  
CTQ596A.Z11   	95383   10-07-93  3/486 Contaq 596-A for 11/11/92  
CTQ596_3.Z06   	92195   03-01-93  386   Contaq 596  
CTQ596_3.Z11    98031  	06-21-93  386   Contaq 596
CTQ596_4.Z06    92236  	03-01-93  486   Contaq 596
CTQ596_4.Z11    97602  	06-21-93  486   Contaq 596
CT596A.Z08   	96217   12-09-93  Contaq 596a  
"
Note, the column of dates is the file date.

**??????    486 EISA chipset [no datasheet]                     <Feb93...
**82C599    PCI-VLB Bridge [no datasheet, some info]                 ?...
**82C693    PCI-ISA Bridge [no datasheet]                            ?...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82495DX/490DX DX CPU-Cache Chip Set                           <Sep91
***Notes:...
***Info:...
***Configurations:...
***Features:
o   50 MHz Intel486 DX CPU 
    - RISC Integer Core with Frequent Instructions Executing in One 
      Clock
    - 160 Mbyte/Sec Burst Bus
    - 41 Dhrystone MIPs
    - 11.5M Double Precision Whetstones/Sec.
    - On-Chip Cache and FPU
o   Highly Flexible
    - Supports 128 Kbyte and 256 Kbyte Configurations
    - Complete MESI Protocol Support
    - 32- or 64-Bit Memory Bus Width
    - Synchronous, Asynchronous, and Strobed Memory Bus Protocols
    - Variable Cache Line Sizes and Sectoring
    - Cache Data Parity Option
o   High Performance Second Level Cache
    - Two-Way Set Associative
    - Write-Back or Write Through Cache
    - Zero Wait State Cache Access
    - Concurrent CPU Bus, Memory Bus, and Internal Array Operation
o   Full Multiprocessing Support
    - Implements MESI Write-Back Cache Protocol
    - Low Bus Utilization
    - Automatically Maintains 1st Level Cache Consistency
    - Supports Read-for-Ownership, Write-Allocation, and Cache-to-
      Cache Transfers

**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...