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**82C591/2 3/486 <Mar92
The BIOS companion. (Croucher, Phil) available here:
https://archive.org/details/pc_engineers_vol1_BIOS
Lists this as:
82C591/82C592 WriteBack
Also listed in:
ftp://ami.com/archive/Other_Manuals/!index.txt
"
CTQ3591.Z12 55546 03-17-92 386 Contaq 82c591 chipset
CTQ4591.Z12 57510 03-17-92 486 Contaq 82c591 chipset
CTQ591A.Z11 84994 02-08-93 3/486 Contact 591-A chipset
"
Indicating there is an A variant of the 82C591, the 82C591A.
**82C593 3/486 [no datasheet] <May92...
**82C596/A 3/486 Writeback Cache [no datasheet] <11/11/92...
**?????? 486 EISA chipset [no datasheet] <Feb93...
**82C599 PCI-VLB Bridge [no datasheet, some info] ?...
**82C693 PCI-ISA Bridge [no datasheet] ?...
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**82495DX/490DX DX CPU-Cache Chip Set <Sep91
***Notes:...
***Info:...
***Configurations:...
***Features:...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
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**IBM AT: MC146818 Real Time Clock <84
***Info:...
***Versions:...
***Features:
o Low-Power, High-Speed, High-Density CMOS
o Internal Time Base and Oscillator
o Counts Seconds, Minutes, and Hours of the Day
o Counts Days of the Week, Date, Month, and Year
o 3 V to 6 V Operation
o Time Base Input Options: 4.194304 MHz, 1.048576 MHz, or 32,768 kHz
o Time Base Oscillator for Parallel Resonant Crystals
o 40 to 200 uW Typical Operating Power at Low Frequency Time Base
o 4.0 to 20 mW Typical Operating Power at High Frequency Time Base
o Binary or BCD Representation of Time, Calendar, and Alarm
o 12- or 24-Hour Clock with AM and PM in 12-Hour Mode
o Daylight Savings Time Option
o Automatic End of Month Recognition
o Automatic Leap Year Compensation
o Microprocessor Bus Compatible [this means absolutely nothing]
o MOTEL Circuit for Bus Univerality
o Multiplexed Bus for Pin Efficiency
o Interfaced with Software as 64 RAM Locations
o 14 Bytes of Clock and Control Registers
o 50 Bytes of General Purpose RAM
o Status Bit Indicates Data Integrity
o Bus Compatible Interrupt Signals (IRQ)
o Three Interrupts are Separately Software Maskable and Testable
Time-of-Day Alarm, Once-per-Second to Once-per-Day
Periodic Rates from 30.5 us to 500 ms
End-of-Clock Update Cycle
o Programmable Square-Wave Output Signal
o Clock Output May Be Used as Microprocessor Clock Input
At Time Base Frequency /1 or /4
o 24-Pin Dual-In-Line Package
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