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*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
**Video:
F64300 Wingine DGX 2MB, (appears to be a VLB version adapted from the proprietary 64200)
F64310 Wingine DGX 2MB (appears to be a PCI version adapted from the proprietary 64200)
OC65540 VGA BIOS c:95
OC65545 VGA BIOS same as 540 but has hardware overlay feature.
94C2001 PUMA (Programmable Universal Micro Accelerator) 50MHz Video accelerator
82C840 8514/A clone
82C9001A Video controller
82C404 Programmable clock synthesizer
82C402 VGA clock Synthesizer
82C411 Flat panel color pallet/DAC
82C425 82C425 CGA, CRT+LCD support, greyscale on LCD, supports two softfonts (up to 8x16 pixels) allowing 512 characters on screen, no snow
82C426 82C426 CGA, CRT, color LCD+AT&T400 support, max 32KB RAM
82C450 82C450 1MB VRAM, max 800x600 256color
82C451 82C451 VGA 256KB DRAM, max 800x600 16color c:90
82C452 82C452 1MB DRAM, max 640x480 256color, 1024x768 16color
82C453 82C453 1MB DRAM, max 800x600 256color
82C455 82C455 256KB DRAM Flat Panel version
82C456, 456A 82C456 256KB DRAM Flat Panel/CRT
82C457 82C457 Full color
82C45x series are VGA
'The 655xx series chips are SVGA video controller chips for flat panel
displays and CRTs. They also provide some level of CGA, MDA, EGA, and
Hercules compatibility, and various accelerator features. They are
designed with various features for reducing power consumption and
optimizing display quality.
source:http://www.igl.ku.dk/~fsp/varia/ct5xx.html
see the above source for more details.
82C481 True-Color Graphics Accelerator Wingine?
F65510 65510 LCD / CRT
F65520 65520 1MB D/VRAM, Full color, max 1280x1024 16color & 800x600 256 color
F65525 65525 LCD / CRT
F65530 65530 1MB D/VRAM, Full color, max 1280x1024 16color & 800x600 256 color, VLB
F65535 65535 LCD / CRT
F65540 65540 same as 65545 but without BitBLT and hw cursor
F65545 65545 mobile, 512-1024KB DRAM, ISA / PCI / VLB
65546 65546
F65548 65548
F65550 65550 HighQV32, mobile, 1-2MB DRAM, PCI / VLB
B65554 65554 HighQV64, mobile, 1-4MB DRAM, BGA
F65555 65555 HighQVPro, mobile, 1-4MB EDO, BGA
F68554 68554 HiQVision
F68555 68555
F69000 69000
M69000 69000 HighQVideo, mobile, 83MHz RAM, 2MB SDRAM on die, PCI / AGPx1, 135MHz RAMDAC, BGA, MiniBGA
F69030 69030 HighQVideo, mobile, 100MHz RAM, 4MB SDRAM on die, PCI / AGPx1, 170MHz RAMDAC, BGA, MiniBGA
*Contaq . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91
***Notes:...
***Info:...
***Features:...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
**82C701 FireStar Plus c:97
***Notes:...
***Info:
Overview
This section describes the follow-on chip to the OPTi FireStar ACPI
solution, the FireStar Plus. The key features of this new product can
be summarized as follows.
o Mostly backward-compatible in pin function and register set with
FireStar ACPI (some PIO functions have been moved from critical
pins to improve timing)
o Implements ATA-33 (Ultra DMA) IDE Interface, with support for all
modes
o Supports 2.5V CPUs
o Incorporates MA13 support for 64Mb SDRAM chips
o Incorporates 64Mb EDO DRAM support
o Enables use of synchronous DRAM on all six banks (original
FireStar chip limited synchronous DRAM to the first four banks)
o Allows redefinition of many interface pins for better utilization
of chipset PIO features (many new function pins are easily
available)
Features
The following paragraphs describe the feature set changes between
FireStar ACPI and FireStar Plus.
Ultra DMA IDE Interface
The ATA33 specification for synchronous bus mastering IDE, also known
as Ultra DMA, is fully supported by FireStar Plus.
Synchronous DRAM on All Banks
The original FireStar chip supports synchronous DRAM only on RAS0-3#.
FireStar Plus also supports synchronous DRAM on RAS4-5#. The
additional functionality is selected through register bits that are
already defined on the FireStar ACPI part.
2.5V CPU Interface
FireStar Plus supports newer CPUs with I/O voltage requirements as low
as 2.5V. The pin redefinition is as follows.
o Pins E8, G5, T5, and W5 are now VCC_CPU and can be powered at 2.5V
or 3.3V.
o Pins K5, H22, and AB19 are now VCC_CORE and must always be powered
at 3.3V.
o Pin M5, CPUCLKIN, must receive a clock on the VCC_CPU plane. So if
a 2.5V CPU is used, this clock should also be 2.5V.
The 2.5V interface is a strap-selected option. It is selected by a
strap on pin B7 (new MA13 pin). If B7 is sensed low at reset, the CPU
interface is 3.3V; if sensed high along with TMS (pin AB5) low, the
CPU interface is 2.5V.
Redefinition of DRQ/DACK# Interface
The 7 pins assigned to DACK0-7# can be redefined to improve avail-
ability of PIO pins.
While the new definition only involves circuit modifications to the
DACK0-7# pins, the overall gain is much greater when used with the
82C602A Companion Chip in its Viper Note-book Mode A configuration.
o 8 power management inputs are now available, muxed in with the
DRQs and IRQ8# on the four EPMMUX pins.
o 7 full-featured PIO pins are available on the former FireStar
DRQ0-7 pins and IRQ8# pin. The number of pins is actually 8, but
is reduced b y 1 because one must be programmed as ATCLK/2.
o 12 PPWR outputs are generated by latching the SD bus lines from
PCTLH (FireStar PPWRL) and PCTLL (FireStar RSTDRV).
o The ISA bus RSTDRV signal is now generated by the 82C602A chip, so
that the FireStar RSTDRV pin can be used for PPWR generation
(power control latch control signal). If the extra PPWR signals
are not needed, the FireStar RSTDRV pin becomes useful as a full-
featured PIO pin.
Warnings
1. Until the Extended Mode option has been programmed, DACK3-7# will
be driving out against the signal input muxes. It is therefore
important to ensure that the logic will not be harmed by this
arrangement (the FireStar outputs safely accept being driven by
external logic in this mode).
2. EDACKEN is an option used to ensure proper ISA master operation.
It prevents the EDACK decoder from glitching its DACK# outputs during
EDACK switching. If ISA masters are not supported in the system, this
option is not needed (tie the EDACK line high on the 82C602A).
3. There are no provisions to block conflicts in case more than one
pin is programmed to the same function. For example, if a PIO pin is
programmed to be ACPI8-11, and the Extended Mode option also enables
EPMMUX1 to bring in ACPI8-11, the results are unpredictable.
***Configurations:...
***Features:...
**82C750 Vendetta [no datasheet] ?...
**82c801 SCWB2 DX Single Chip Solution c:92...
**82C802 SCWB2 PC/AT Single Chip [no datasheet] ?...
**82C802G/GP System/Power Management Controller (cached) c:93...
**82C895 System/Power Management Controller (cached) c:Sep94...
**82C898 System/Power Management Controller (non-cache)c:Nov94...
**
**Support Chips:
**82C601/2 Buffer Devices <Nov94...
**82C822 PCIB (VLB-to-PCI bridge) c:94...
**Other:...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
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*TI (Texas Instruments)...
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*Unresearched:...
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