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**82C710 Universal Peripheral Controller c:Aug90
***Info:...
***Versions:...
***Features:
o Low Power CMOS, 100pin PQFP Package
o On Chip Power Management Features, Controllable Through Hardware
and/or Software
o 100% IBM PC-XT/AT Compatibility.
o 24 mA IBM AT/XT Bus Interface Buffers
o Schmitt Trigger Input on Reset Pin
o 1 x 16450 Compatible UART
o 1 IBM PC-XT/AT Compatible Enhanced (Bi-Directional) Parallel Port
o 24 mA Parallel Port Output Drivers
o IDE Interface (For Embeded AT & XT Hard drives)
o General Purpose Chip Select
o Real Time Clock chip Select
o Fully uPD72065B and IBM-BIOS Compatible Floppy Disk Controller
- Licensed NEC design
- 48 mA floppy drive interface buffers
- Data rate and drive control registers
- Two pin programmable precompensation modes
- Supports two floppy drives directly and up to four with an
external decoder
- DMA enable logic
o On-Chip Precision Analog Data Separator
- +/-380ns at 500K bps
- +/-740ns at 250K bps
- Automatically selects one of three filters
- Supports 250 Kb/s, 300 Kb/s, 500 Kb/s & 1 Mb/s data rates
o Single 24 MHz Crystal/Oscillator for UART and Floppy Disk
Controller
**82C711 Universal Peripheral Controller II c:Jan91...
**82C712 Universal Peripheral Controller II c:Jan91...
**82C721 Universal Peripheral Controller III c:May93...
**82C735 I/O Peripheral Controller With Printgine c:Jul93...
**82C835 Single CHIP 386sx AT Cache Controller c:Apr91...
**F87000 Multi-Mode Peripheral Chip 11/23/93...
**Other:...
**Disk:...
**Video:...
*Contaq . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91
***Notes:...
***Info:
The Intel 82495XP cache controller and 82490XP cache RAM, when coupled
with a user-implemented memory bus controller, provide a second-level
cache subsystem that eliminates the memory latency and bandwidth
bottleneck for a wide range of multiprocessor systems based on the
i860 XP microprocessor. The CPU interface is optimized to serve the
i860 XP microprocessor with zero wait states at up to 50 MHz. A
secondary cache built from the 82495XP and 82490XP isolates the CPU
from the memory subsystem; the memory can run slower and follow a
different protocol than the i860 XP microprocessor.
***Features:...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
**SN74LS610/2 IBM AT: SN74LS610, SN74LS612 Memory Mappers <84
***Notes:...
***Info:...
***Versions:...
***Features:...
**TACT82000 3-Chip 286 [no datasheet] c89...
**TACT82411 Snake Single-Chip AT Controller c90...
**TACT82S411 Snake+ Single-Chip AT Controller [no datasheet] c91...
**TACT83000 AT 'Tiger' Chip Set (386) c89...
**TACT84500 AT Chip Set (486, EISA) [no datasheet, some info] c91...
**Other:...
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