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**????? (Profusion) c:99
Chips:
Memory Access Controller (MAC)
Data Interface Buffer (DIB)
CPUs: 8x P-III Xeon Oct
DRAM Types: SDRAM PC100 2-way Interleave dual channel
Max Mem: 32GB
ECC/Parity: ECC
AGP speed: N/A
Bus Speed: 100
PCI Clock/Bus: 1/3 PCI-66/64
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
**HMC82C206 Integrated Peripherals Controller (10MHz C&T 82c206) ?
***Info:...
***Versions:...
***Features...
*Logicstar...
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*OPTi...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
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*Unresearched:...
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*Western Digital...
*Winbond...
**W83777F/87F Power I/O (Multi I/O) <95
***Info:...
***Versions:...
***Features:...
**W83877F WINBOND I/O (Multi I/O) <96...
**W83877TF/TG/TD WINBOND I/O (Multi I/O) c97...
**W83977F/G/AF/AG WINBOND I/O (Multi I/O) c97...
**W83977TF WINBOND I/O (Multi I/O) c97...
**W83977EF WINBOND I/O (Multi I/O) <98...
**W83977ATF WINBOND I/O (Multi I/O) <98...
**
**Disk Controller:
**W83759/A/F/AF Advanced VL-IDE Disk Controller <96...
**W83769 Local Bus IDE Solution <94...
**
**UARTS:
**W86C250A UART (equivalent of INS8C250A) [no datasheet]
**W86C450/P Universal Asynchronous Receiver/Transmitter <Jul89...
**W86C451 I/O controller for IBM PC/AT/XT <Jul89...
**W86C452 I/O controller for IBM PC/AT Jul89...
**W86C456 I/O controller [no datasheet] ?
**W860551/P UART with FIFO and Printer Port Controller <94
***Info:...
***Versions:...
***Features:
o Easily interfaces with most popular microprocessors
o Pin compatible and functionally compatible with the existing
W860451
o Centronics parallel interface
o Capable of running all existing 16450 and 16550 software
o Uses system's 14.3181 BMHz clock input
o In FIFO mode transmitter and receiver are each buffered with
16-byte FIFOs to reduce number of intercepts presented to the CPU
o Adds or deletes standard asynchronous communication bits (start,
stop, and parity) to or from serial data
o Independently controlled transmit, receive, line status, and data
set interrupts
o Programmable baud rate generator
o Modem control functions (CTS, RTS, DSR, DTR, RI, and DCD)
o Fully programmable serial-interface characteristics:
- 5, 6, 7, or 8-bit characters
- Even, odd, or no-parity bit generation and detection
- 1, 1.5, or 2-stop bit generation
- Baud generation
o False start bit detection
o Internal diagnostic capabilities:
- Loopback controls for communications link fault isolation
- Break, parity, overrun, framing error simulation
o Fully prioritized interrupt system controls
o 40-pin PDIP package for W860551 and 44-pin PLCC package for
W86C551P
**
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*ZyMOS...
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