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**82485 Turbo Cache (and 485Turbocache) c90
***Notes:...
***Info:...
***Versions:...
***Features:...
**82489DX Advanced Programmable Interrupt Controller 10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
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**82C822 PCIB (VLB-to-PCI bridge) c:94
***Notes:...
***Info:...
***Versions:...
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**Other:...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
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*Unresearched:...
*VIA...
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*Winbond...
**W83628F/29D PCI TO ISA Bridge Set c98
***Info:...
***Configurations:...
***Features:...
**W83626F/D LPC TO ISA Bridge Set <00...
**
**Multi I/O:
**W83757 SUPER I/O CHIP <92...
**W83767F ?? Multi I/O [no datasheet]
**W83777F/87F Power I/O (Multi I/O) <95...
**W83877F WINBOND I/O (Multi I/O) <96...
**W83877TF/TG/TD WINBOND I/O (Multi I/O) c97...
**W83977F/G/AF/AG WINBOND I/O (Multi I/O) c97...
**W83977TF WINBOND I/O (Multi I/O) c97...
**W83977EF WINBOND I/O (Multi I/O) <98...
**W83977ATF WINBOND I/O (Multi I/O) <98...
**
**Disk Controller:
**W83759/A/F/AF Advanced VL-IDE Disk Controller <96...
**W83769 Local Bus IDE Solution <94...
**
**UARTS:
**W86C250A UART (equivalent of INS8C250A) [no datasheet]
**W86C450/P Universal Asynchronous Receiver/Transmitter <Jul89...
**W86C451 I/O controller for IBM PC/AT/XT <Jul89
***Info:
GENERAL DESCRIPTION
The W860451 is an enhanced version of the popular W860450 asynchronous
communication element (ACE) fabricated using WINBOND'S CMOS process.
The device supports one serial-to-parallel conversion on data
characters received from a peripheral device or a MODEM. and
parallel-to-serial conversion on data characters received from the
CPU. The CPU can read the complete status of the UART at any time
during the functional operation. Status information reported includes
the type and condition of the transfer operations being performed by
the UART as well as any error conditions (parity, overrun, framing. or
break interrupt). The UART includes a programmable baud rate
generator that is capable of dividing the timing reference clock input
by divisors of 1 to (2^16 - 1), and producing a 16x clock for driving
the internal transmitter logic. Provisions are also included to use
this 16x clock to drive the receiver logic. The UART includes a
complete MODEM-control capability and a processor-interrupt system.
interrupts can be programmed to the user’s requirements, minimizing
the computing required to handle the communications link. In addition
to its communication interface capabilities, the W860451 provides the
user with a parallel Centronics type printer.
***Versions:...
***Features:...
**W86C452 I/O controller for IBM PC/AT Jul89...
**W86C456 I/O controller [no datasheet] ?
**W860551/P UART with FIFO and Printer Port Controller <94...
**
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