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**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94
***Notes:...
***Info:
The 82497 Cache Controller and multiple 82492 Cache SRAMs combine with
the Pentium processor  (735\90, 810\100) to form a  CPU Cache chip set
designed for high performance servers and function-rich desktops.  The
high-speed interconnect between the  CPU and cache components has been
optimized to  provide zero-wait state  operation. This CPU  Cache chip
set  is fully  compatible with  existing  software, and  has new  data
integrity features for mission critical applications.

The 82497 cache controller implements the MESI write-back protocol for
full multiprocessing support. Dual  ported buffers and registers allow
the 82497  to concurrently  handle CPU bus,  memory bus,  and internal
cache operation for maximum performance.

The  82492 is a  customized high-performance  SRAM that  supports 32-,
64-, 128-bit wide memory bus widths, 16-, 32-, and 64-byte line sizes,
and optional sectoring.  The data path between the  CPU bus and memory
bus  is separated  by the  82492, allowing  the CPU  bus  to handshake
synchronously,  asynchronously,  or   with  a  strobed  protocol,  and
allowing concurrent CPU bus and memory bus operations.

***Configurations:...
***Features:...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
**800 series...
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**5595       Pentium PCI System I/O                          <12/24/97
***Notes:...
***Info:...
***Versions:...
***Features:...
**950        LPC I/O                                         <07/16/99...
**Other:...
**PII/III/Pro...
**Athlon etc...
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**W83757          SUPER I/O  CHIP                                  <92
***Info:...
***Versions:...
***Features:
o   Compatible with IBM PC AT/XT Disk Drive systems.
o   Supports up to two 3.5", or 5.25“ 360K/720K/ 1.2M or 1.44M Floppy 
    Disk Drives.
o   Emulates NEC765A in IBM environment.
o   Supports variable write precompensation with track selectable 
    capability.
o   Built-in address mark detection circuit to simplify the read 
    electronics.
o   IBM PC system address decoder.
o   Supports up to two Embedded Hard Disk Drives (IDE AT bus).
o   Single 24 MHz crystal input.
o   Fully programmable serial-interface characteristics:
    - 5, 6, 7 or 8-bit characters.
    - even, odd or no parity bit generation and detection
    - 1, 1.5 or 2 stop bit generation.
o   Internal diagnostic capabilities:
    - loopback control for communications link fault isolation
    - break, parity, overrun, framing error simulation.
o   Programmable baud rate generator allows division of any input 
    clock 
    by 1 to (2^16-1) and generates the internal 16 X clock.
o   Compatible with IBM printer port.
o   2u high performance CMOS technology.
o   100-pin QFP.

**W83767F         ??           Multi I/O  [no datasheet]
**W83777F/87F     Power I/O   (Multi I/O)                          <95...
**W83877F         WINBOND I/O (Multi I/O)                          <96...
**W83877TF/TG/TD  WINBOND I/O (Multi I/O)                          c97...
**W83977F/G/AF/AG WINBOND I/O (Multi I/O)                          c97...
**W83977TF        WINBOND I/O (Multi I/O)                          c97...
**W83977EF        WINBOND I/O (Multi I/O)                          <98...
**W83977ATF       WINBOND I/O (Multi I/O)                          <98...
**
**Disk Controller:
**W83759/A/F/AF   Advanced VL-IDE Disk Controller                  <96...
**W83769          Local Bus IDE Solution                           <94...
**
**UARTS:
**W86C250A  UART (equivalent of INS8C250A) [no datasheet]
**W86C450/P Universal Asynchronous Receiver/Transmitter         <Jul89...
**W86C451   I/O controller for IBM PC/AT/XT                     <Jul89...
**W86C452   I/O controller for IBM PC/AT                         Jul89...
**W86C456   I/O controller [no datasheet]                            ?
**W860551/P UART with FIFO and Printer Port Controller             <94...
**
**Other:...
*ZyMOS...
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