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**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91
***Notes:...
***Info:...
***Features:...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
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**SN74LS610/2 IBM AT: SN74LS610, SN74LS612 Memory Mappers          <84
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**TACT82000   3-Chip 286 [no datasheet]                            c89...
**TACT82411   Snake  Single-Chip AT Controller                     c90...
**TACT82S411  Snake+ Single-Chip AT Controller [no datasheet]      c91...
**TACT83000   AT 'Tiger' Chip Set (386)                            c89...
**TACT84500   AT Chip Set (486, EISA) [no datasheet, some info]    c91...
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*Western Digital...
**WD7625     Desktop Buffer Manager                          <10/01/92
***Info:...
***Versions:...
***Features:
ADDRESS BUFFER FEATURES
o   Allows WD7SC10A, WD7855, WD8110, WD7710, and WD7910 based designs 
    with WD7620/30 for laptop or notebook systems
o   Will work in three different power supply modes:
    - 3.3V only
    - 5V only
    - Mix mode 3.3V and 5V
o   Direct connect to AT Address Bus SA1:19 and LA17:23 with 24 mA 
    drive
o   Power Management Control (PMC) input MUX 
o   General purpose suspend/resume and power supply control logic
o   Fifteen-bit Power Management Control (PMC) output register and 
    control logic
o   Low power request and resume signal delay simplify the design of 
    the power supply
o   Watchdog timer for system idle detection
o   DRAM WE signal from WD7xc10 inversion and buffering
o   RESIN output generation from reset switch (RSTSW)
o   System Reset generation
o   Chip select decoding for registers in the WD7625LV Data Buffer 
    Function
o   144-pin SQFP package

DATA BUFFER FEATURES
o   Allows WD7SC10A, WD7855, WD7710, and WD7910 based designs with 
    WD7620/30 for laptop or notebook systems
o   Will work in three different power supply modes:
    - 3.3V only
    - 5V only
    - Mix mode 3.3V and 5V
o   Direct connection to AT data bus; 20K integrated pull-up for 
    SD(0:7)
o   Direct connection to IDE data bus
o   Two general purpose 8-bit I/O registers:
    - Register A
    - Register B
o   One general purpose 8-bit I/O Register C, with single bit 
    set/reset control
o   One general purpose 1-bit I/O Register Y0
o   One 4-bit general purpose input only Register Z
o   DRQ multiplexing plus 20K integrated pull-down
o   DACK demultiplexing
o   SMEMR, SMEMW signals plus 22K internal pull-up
o   144-pin SOFP package

**WD8120LV   Super I/O [no datasheet]                                ?
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