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**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94
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**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
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**85C206     Integrated Peripheral Controller [no datasheet]         ?
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**5595       Pentium PCI System I/O                          <12/24/97...
**950        LPC I/O                                         <07/16/99...
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**WD7625     Desktop Buffer Manager                          <10/01/92
***Info:
INTRODUCTION
This document describes the two separate functions, Address Buffer and
Data Buffer,  available in  the WD7625LV chip.  A strapping  input pin
selects  the Data  Buffer  Function when  strapped  low, otherwise  it
selects the Address Buffer Function.

GENERAL DESCRIPTION
The  WD7625LV is  a  combination design  which  includes two  separate
functions: Address  Buffer and Data  Buffer in one chip.   A strapping
input pin  selects the  Data Buffer  Function if  it is  strapped low;
otherwise, it  selects the Address  Buffer Function. For  designs that
use  both  the data  buffer  and  the  address buffer  functions,  two
WD7625LV devices are needed in the system.

In the Address Buffer Function,  the WD7625LV is an address buffer and
power management chip.  

In the Data Buffer Function, the WD7625LV is a data buffer, IDE buffer
and I/O register device for the WD7x00 16-bit chip sets.
***Versions:...
***Features:
ADDRESS BUFFER FEATURES
o   Allows WD7SC10A, WD7855, WD8110, WD7710, and WD7910 based designs 
    with WD7620/30 for laptop or notebook systems
o   Will work in three different power supply modes:
    - 3.3V only
    - 5V only
    - Mix mode 3.3V and 5V
o   Direct connect to AT Address Bus SA1:19 and LA17:23 with 24 mA 
    drive
o   Power Management Control (PMC) input MUX 
o   General purpose suspend/resume and power supply control logic
o   Fifteen-bit Power Management Control (PMC) output register and 
    control logic
o   Low power request and resume signal delay simplify the design of 
    the power supply
o   Watchdog timer for system idle detection
o   DRAM WE signal from WD7xc10 inversion and buffering
o   RESIN output generation from reset switch (RSTSW)
o   System Reset generation
o   Chip select decoding for registers in the WD7625LV Data Buffer 
    Function
o   144-pin SQFP package

DATA BUFFER FEATURES
o   Allows WD7SC10A, WD7855, WD7710, and WD7910 based designs with 
    WD7620/30 for laptop or notebook systems
o   Will work in three different power supply modes:
    - 3.3V only
    - 5V only
    - Mix mode 3.3V and 5V
o   Direct connection to AT data bus; 20K integrated pull-up for 
    SD(0:7)
o   Direct connection to IDE data bus
o   Two general purpose 8-bit I/O registers:
    - Register A
    - Register B
o   One general purpose 8-bit I/O Register C, with single bit 
    set/reset control
o   One general purpose 1-bit I/O Register Y0
o   One 4-bit general purpose input only Register Z
o   DRQ multiplexing plus 20K integrated pull-down
o   DACK demultiplexing
o   SMEMR, SMEMW signals plus 22K internal pull-up
o   144-pin SOFP package

**WD8120LV   Super I/O [no datasheet]                                ?
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