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**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94
***Notes:...
***Info:
The 82497 Cache Controller and multiple 82492 Cache SRAMs combine with
the Pentium processor  (735\90, 810\100) to form a  CPU Cache chip set
designed for high performance servers and function-rich desktops.  The
high-speed interconnect between the  CPU and cache components has been
optimized to  provide zero-wait state  operation. This CPU  Cache chip
set  is fully  compatible with  existing  software, and  has new  data
integrity features for mission critical applications.

The 82497 cache controller implements the MESI write-back protocol for
full multiprocessing support. Dual  ported buffers and registers allow
the 82497  to concurrently  handle CPU bus,  memory bus,  and internal
cache operation for maximum performance.

The  82492 is a  customized high-performance  SRAM that  supports 32-,
64-, 128-bit wide memory bus widths, 16-, 32-, and 64-byte line sizes,
and optional sectoring.  The data path between the  CPU bus and memory
bus  is separated  by the  82492, allowing  the CPU  bus  to handshake
synchronously,  asynchronously,  or   with  a  strobed  protocol,  and
allowing concurrent CPU bus and memory bus operations.

***Configurations:...
***Features:...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
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**85C206     Integrated Peripheral Controller [no datasheet]         ?
***Notes:...
**5595       Pentium PCI System I/O                          <12/24/97...
**950        LPC I/O                                         <07/16/99...
**Other:...
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**WD7615     Desktop Buffer Manager                          <04/15/92
***Info:...
***Versions:...
***Features:
o   Allows the WD7XC10 based designs to work with a generic "Super l/O" 
    device or with the WD76C20 and WD76C30
o   Replaces majority of external "glue" logic, up to 13 devices:
    - AT bus address buffers with 24 mA drive
    - AT bus interrupt multiplexing, and interrupt pull ups.
    - AT bus DRQ multiplexing and internal pull downs.
    - Keyboard/mouse interrupt latching and clearing functions
    - A20 Gate logic
    - Controlling the IDE data bit 7 at address 3F7H.
o   Allows implementation of a desktop system with only three external 
    devices
o   Direct connect to AT address bus SA1 through SA19 and LA17 through 
    LA23 with 24 mA drive
o   DAC multiplexing and RESET generation
o   DRAM WE signal from WD76C10 inversion and buffering
o   SMEMR and SMEMW generation with 24mA direct drive
o   Divide by 2 or divide by 4 clock output
o   136-pin MQFP package



**WD7625     Desktop Buffer Manager                          <10/01/92...
**WD8120LV   Super I/O [no datasheet]                                ?
**Other Chips:...
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