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**A note on VESA support of 486 chipsets.
Many chipsets state  that they support VESA local  bus.  In some cases
these actually  implement VLB somewhat  like PCI, where it  is entirly
decoupled from the CPU bus. Chipsets  that do not state they work with
VLB,  may  be found  on  motherboards  that  contain VLB  slots.   VLB
is  *basically*  The 486  CPU  pinout in  a  slot  form. Unless  these
m/boards contain  some additional  chips, there VLB  implementation is
directly coupled to the CPU.

**Datasheets:...
*_IBM...
*ACC Micro...
*ALD...
*ALi...
*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
*Contaq  . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82489DX       Advanced Programmable Interrupt Controller    10/12/92
***Notes:...
***Info:...
***Versions:...
***Features:...
**82495DX/490DX DX CPU-Cache Chip Set                           <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
**WD7615     Desktop Buffer Manager                          <04/15/92
***Info:...
***Versions:...
***Features:
o   Allows the WD7XC10 based designs to work with a generic "Super l/O" 
    device or with the WD76C20 and WD76C30
o   Replaces majority of external "glue" logic, up to 13 devices:
    - AT bus address buffers with 24 mA drive
    - AT bus interrupt multiplexing, and interrupt pull ups.
    - AT bus DRQ multiplexing and internal pull downs.
    - Keyboard/mouse interrupt latching and clearing functions
    - A20 Gate logic
    - Controlling the IDE data bit 7 at address 3F7H.
o   Allows implementation of a desktop system with only three external 
    devices
o   Direct connect to AT address bus SA1 through SA19 and LA17 through 
    LA23 with 24 mA drive
o   DAC multiplexing and RESET generation
o   DRAM WE signal from WD76C10 inversion and buffering
o   SMEMR and SMEMW generation with 24mA direct drive
o   Divide by 2 or divide by 4 clock output
o   136-pin MQFP package



**WD7625     Desktop Buffer Manager                          <10/01/92...
**WD8120LV   Super I/O [no datasheet]                                ?
**Other Chips:...
*Winbond...
*ZyMOS...
*General Sources:...