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**82495DX/490DX DX CPU-Cache Chip Set                           <Sep91
***Notes:...
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**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91
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***Features:...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
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**WD7900/LP/LV  System Chip Set for 80286 or 80386SX (Cache) <11/25/91
***Notes:...
***Info:
****General:...
****WD7910/LP/LV (System Controller):
INTRODUCTION
The WD7910 is  the second generation single chip  AT solution based on
the WD76C10A  core. It is fabricated  in 0.9 micron  CMOS.  The WD7910
provides  8  Kbytes  of   direct-mapped  or  two-way  set  associative
lookaside caching, a  page-interleaved memory controller, and enhanced
power management features.  Figure 1-1 [see datasheet] shows the block
diagram of the WD7910-based system.

The  standard  version  of  the  WD7910 operates  from  5  VDC  (±10%)
supplies. An extended lowpower version, the WD7910lP, can operate with
3.3 VDC (±0.3V) or 5 VDC (±0.5V).

GENERAL DESCRIPTION
The  WD7910 is  designed  for use  in  a high  performance desktop  AT
computer  using  an 80286  or  80386SX processor  up  to  25 MHz.  The
WD7910LP has the features of the  WD7910 and is designed to operate in
a  high-performance notebook/laptop  AT compatible  computer  using an
80286 or 80386SX processor.

WD7910
The WD7910  contains a high  performance memory controller  with prog-
rammable  modes of operation.  It supports  non-page, zero  wait state
read and write memory control. A maximum of four banks of 64 Kbit, 256
Kbit, 1 Mbit, 4 Mbit or 16 Mbit DRAM may be controlled, allowing up to
16 Mbytes  of real  or 32 Mbytes  EMS (Expanded  Memory Specification)
memory. Any combination  of DRAM sizes may be  used.  In addition, the
WD7910 controls  page mode DRAM or  static column DRAM  with page mode
operation.

The on-board memory can be  allocated either to extended or EMS memory
in  128  Kbyte  increments.   Forty  EMS  registers  support  EMS  4.0
multitasking.

An  internal self-tuning delay  line is  used for  DMA and  Bus Master
memory  cycles. Delay  line information  is  also used  to adjust  the
strength of  the output drivers.  This stabilizes the output  rise and
fall   times,   which  reduces   ground   noise  and   electromagnetic
interference (EMI).

EMS access  to external  RAM or ROM  may be  used to support  Kanji or
other extended character sets.

The WD7910 interfaces  with either an 80286 or  80386SX processor. The
processor type is automatically sensed  at power-up. No extra logic is
required  to interface with  the 80386SX.  The variation  in processor
reset propagation delay is controlled  to meet the strict reset timing
of the 80386SX.

WD7910LP
In addition to supporting all the features of the WD7910, the WD7910LP
also  supports  portable notebook/laptop  computers.  To provide  this
support, the WD7910LP makes use  of Power Management Control (PMC) for
powering down  peripherals or the processor,  which includes processor
stop  clock, slow  clock,  automatic processor  clock speed  switching
modes and CAS before RAS slow refresh. Suspend and resume is supported
when low power  DRAM is refreshed while the  processor and other power
consuming devices are  turned off. The power drain  for the core logic
and VGA  controller is less  than 5 mA  in this mode. Power  and clock
speed may  be controlled by  the keyboard processor,  transparently to
the 80286 or 80386SX.

The  System   Activity  Monitor  (SAM)  provided  by   WD7910LP  is  a
transparent feature  that replaces the  functions previously performed
by  software.  It determines  when  the system  has  been  idle for  a
previously  programmed period  of time  and determines  a  clean break
point in which to perform powerdown activities such as suspend.

The  WD7910lP also  supports  System Management  Interrupt (SMI)  with
complete I/O trapping of up to six separate I/O ranges.

     ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

VLBI Control
The Video local  Bus Interface (VLBI) control is  internal logic which
interfaces with  the WD90C56  VLBI controller. It  has the  ability to
determine whether  the current  CPU cycle should  be processed  by the
WD90C56 or the WD7910LP.


****Other Chips:...
***Configurations:...
***Features:...
**WD8110        System controller for 80386DX/486            <11/30/93...
**
**Support Chips:
**WD76C20x   Floppy, RTC, IDE and Support Logic Device       <11/25/91...
**WD76C30x   Perip. Ctrl, Interrupt Multiplex, and Clock Gen <11/18/91...
**WD7615     Desktop Buffer Manager                          <04/15/92...
**WD7625     Desktop Buffer Manager                          <10/01/92...
**WD8120LV   Super I/O [no datasheet]                                ?
**Other Chips:...
*Winbond...
*ZyMOS...
*General Sources:...